Sleep Transistors to Improve the Process Variability and Soft Error Susceptibility

This paper evaluates the potential of using the sleep transistor in FinFET logic cells to mitigate the process variability effects and the soft error susceptibility. The insertion of a sleep transistor improves up to 40.6% the delay variability and up to 12.4% the power variability. Moreover, the design with a sleep transistor became all logic cells investigated free of faults, independently of the supply voltage applied in the design.

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