The M/sup 2/ hierarchical multiprocessor

The design and development of a bus-based hierarchical multiprocessor named M/sup 2/ is discussed. The primary design goal of the M/sup 2/ was to derive a multiprocessor architecture that features a much higher degree of scalability than the shared-memory shared-bus architecture and exploits parallelism at both medium- and coarse-grain levels. Compared with other hierarchical multiprocessors, the M/sup 2/ is distinctive in its memory configuration, which is aimed at avoiding severe inter-CPU interference due to page-swapping events. Compared with a group of multiprocessors connected by a local area network, the M/sup 2/ enjoys higher scalability due to higher bandwidth of the backplane bus.<<ETX>>