Efficient reconfiguration of 2-D rectangular systolic arrays
暂无分享,去创建一个
[1] Benjamin W. Wah,et al. Guest Editors' Introduction: Systolic Arrays-From Concept to Implementation , 1987, Computer.
[2] Mariagiovanna Sami,et al. Fault Tolerance Techniques for Array Structures Used in Supercomputing , 1986, Computer.
[3] Sy-yen Kuo,et al. Efficient Spare Allocation for Reconfigurable Arrays , 1987, IEEE Design & Test of Computers.
[4] H. T. Kung. Why systolic architectures? , 1982, Computer.
[5] Jacob A. Abraham,et al. LBW COST SCEEMES FOR FAULT TOLEEANCE IN MATRIX OPERATIONS WITH PROCESSOR ARRAYS , 1982 .
[6] Renato Stefanelli,et al. Reconfigurable architectures for VLSI processing arrays , 1986 .
[7] Mariagiovanna Sami,et al. Reconfigurable architectures for VLSI processing arrays , 1983, Proceedings of the IEEE.
[8] José A. B. Fortes,et al. A taxonomy of reconfiguration techniques for fault-tolerant processor arrays , 1990, Computer.
[9] H. T. Kung,et al. Fault-Tolerance and Two-Level Pipelining in VLSI Systolic Arrays , 1983 .
[10] W. Kent Fuchs,et al. Efficient Spare Allocation for Reconfigurable Arrays , 1987 .
[11] Nitin Hemant Vaidya,et al. Low-cost schemes for fault tolerance , 1993 .
[12] Israel Koren,et al. Fault tolerance in VLSI circuits , 1990, Computer.
[13] Sudhakar M. Reddy,et al. On the Design of Fault-Tolerant Two-Dimensional Systolic Arrays for Yield Enhancement , 1989, IEEE Trans. Computers.
[14] D.K. Pradhan,et al. Yield and performance enhancement through redundancy in VLSI and WSI multiprocessor systems , 1986, Proceedings of the IEEE.