PVD TiN metal gate MOSFETs on bulk silicon and fully depleted silicon-on-insulator (FDSOI) substrates for deep sub-quarter micron CMOS technology

We report here for the first time an evaluation of a polysilicon capped physical vapor deposited (PVD) titanium nitride (TiN) metal gate integration on sub-quarter micron CMOSFETs using bulk Si and FDSOI substrates. In addition to eliminating poly depletion effects and lowering gate line resistance, the use of the TiN gate enables lower Vt when used with FDSOI substrates instead of bulk Si. Excellent on-off and short channel characteristics can be obtained with the TiN gate. Issues associated with Leff and reliability are also discussed.

[1]  Tadahiro Ohmi,et al.  Tantalum-gate thin-film SOI nMOS and pMOS for low-power applications , 1997 .

[2]  G.A. Brown,et al.  A comparison of TiN processes for CVD W/TiN gate electrode on 3 nm gate oxide , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[3]  Percy V. Gilbert,et al.  A 0.25 /spl mu/m CMOS technology with 45 /spl Aring/ NO-nitrided oxide , 1995, Proceedings of International Electron Devices Meeting.

[4]  Mark E. Law,et al.  The effects of strain on dopant diffusion in silicon , 1993, Proceedings of IEEE International Electron Devices Meeting.

[5]  Chenming Hu.  Gate oxide scaling limits and projection , 1996, International Electron Devices Meeting. Technical Digest.

[6]  J.D. Bude,et al.  Gate capacitance attenuation in MOS devices with thin gate dielectrics , 1996, IEEE Electron Device Letters.

[7]  A. Chatterjee,et al.  Feasibility of using W/TiN as metal gate for conventional 0.13 /spl mu/m CMOS technology and beyond , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[8]  D. Lee,et al.  Gate oxide integrity (GOI) of MOS transistors with W/TiN stacked gate , 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.