Collaborative voltage scaling with online STA and variable-latency datapath

This paper presents an event-driven adaptive voltage scaling (AVS) system, where a vanguard collaborates with a rearguard to find a minimal supply voltage. While the vanguard is responsible for the slack cycle time estimation, the rearguard allows voltage over-scaling with a variable-latency datapath. An improved vanguard is proposed based on online static timing analysis (STA), which monitors a scalable number of critical path candidates at run time. In our simulations, the delay estimation error is within 10%, which is relatively small compared to critical path variations of prevailing multi-Vt designs in deep-submicron era. A testchip with a 32-bit tiny RISC has been fabricated with the TSMC 65nm LP process technology to demonstrate the effectiveness.

[1]  Tadahiro Kuroda,et al.  Variable supply-voltage scheme for low-power high-speed CMOS digital design , 1998, IEEE J. Solid State Circuits.

[2]  Changhae Park,et al.  Reversal of temperature dependence of integrated circuits operating at very low voltages , 1995, Proceedings of International Electron Devices Meeting.

[3]  Yong-Bin Kim,et al.  A high-efficiency fully digital synchronous buck converter power delivery system based on a finite-state machine , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Sanjay Pant,et al.  A self-tuning DVS processor using delay-error detection and correction , 2005, IEEE Journal of Solid-State Circuits.

[5]  Gu-Yeon Wei,et al.  ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency , 2008, 2008 International Symposium on Computer Architecture.

[6]  David Blaauw,et al.  Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation , 2003, MICRO.

[7]  Dragan Maksimovic,et al.  Closed-loop adaptive voltage scaling controller for standard-cell ASICs , 2002, ISLPED '02.

[8]  Robert C. Aitken,et al.  Low Power Methodology Manual - for System-on-Chip Design , 2007 .

[9]  Alice Wang,et al.  Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice , 2008 .

[10]  Gu-Yeon Wei,et al.  Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency , 2009, IEEE Micro.

[11]  Anantha Chandrakasan,et al.  Embedded power supply for low-power DSP , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[12]  Soraya Ghiasi,et al.  A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[13]  Manoj Sachdev,et al.  Efficient adaptive voltage scaling system through on-chip critical path emulation , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[14]  Luca Benini,et al.  Telescopic units: a new paradigm for performance optimization of VLSI designs , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[16]  Shih-Chieh Chang,et al.  An Efficient Mechanism for Performance Optimization of Variable-Latency Designs , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[17]  Thomas D. Burd,et al.  Energy efficient microprocessor design , 2001 .

[18]  V. von Kaenel,et al.  A voltage reduction technique for battery-operated systems , 1990 .

[19]  R. Brayton,et al.  Yield maximization and worst-case design with arbitrary statistical distributions , 1980 .

[20]  Steve Furber.  ARM System-on-Chip Architecture , 2000 .

[21]  Enrico Macii,et al.  Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits , 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).