The necklace-hypercube: a well scalable hypercube-based interconnection network for multiprocessors

In this paper, we introduce a new interconnection network, namely the necklace-hypercube, based on the binary cube with an array of processors (as a necklace of processors) attached to each two adjacent nodes of the hypercube network. Topological properties of the proposed network are studied. Some important basic operations such as optimal routing and VLSI layout in necklace-hypercubes are also addressed here. Moreover, a comparison between the necklace-hypercube and some other popular networks is conducted. The comparison is based on VLSI layout, scalability, and other static topological properties. Area-efficient VLSI layout and network scalability of the necklace-hypercube make it an attractive alternative to the well-known hypercube network topology, while keeping most of desirable properties of the hypercube.

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