论文信息 - Optimizing Power in ASIC Behavioral Synthesis

Optimizing Power in ASIC Behavioral Synthesis

Attacking power consumption at the behavioral level exploits an application's inherent parallelism to maintain performance while compensating for slower, less power-hungry operators. The authors' method and tool optimize and evaluate the effects of power-saving strategies on performance and silicon area.

John P. Knight | Raul San Martin | R. S. Martin | J. Knight

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