Area-Time Complexities of Multi-Valued Decision Diagrams
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[1] Tiziano Villa,et al. Multi-valued decision diagrams: theory and applications , 1998 .
[2] Tsutomu Sasao,et al. A method to represent multiple-output switching functions by using multi-valued decision diagrams , 1996, Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96).
[3] Luciano Lavagno,et al. Synthesis of Software Programs for Embedded Control Applications , 1999, 32nd Design Automation Conference.
[4] Rolf Drechsler,et al. Implementing a multiple-valued decision diagram package , 1998, Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138).
[5] Sharad Malik,et al. Fast functional simulation using branching programs , 1995, ICCAD.
[6] Rolf Drechsler,et al. Efficient graph based representation of multi-valued functions with an application to genetic algorithms , 1994, Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94).
[7] Shinobu Nagayama,et al. Compact BDD Representations for Multiple-Output Functions and Their Application , 2001 .
[8] F. Brglez,et al. A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .
[9] Tsutomu Sasao. Compact SOP representations for multiple-output functions-an encoding method using multiple-valued logic , 2001, Proceedings 31st IEEE International Symposium on Multiple-Valued Logic.
[10] Rolf Drechsler,et al. Using lower bounds during dynamic BDD minimization , 1999, DAC '99.
[11] Felix Schlenk,et al. Proof of Theorem 3 , 2005 .
[12] Tsutomu Sasao,et al. A hardware simulation engine based on decision diagrams , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).
[13] Tsutomu Sasao,et al. Implementation of multiple-output functions using PQMDDs , 2000, Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000).
[14] Tsutomu Sasao,et al. Switching Theory for Logic Synthesis , 1999, Springer US.
[15] Pierre Marchal,et al. Field-programmable gate arrays , 1999, CACM.
[16] C. Thomborson,et al. Area-time complexity for VLSI , 1979, STOC.
[17] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[18] Hiroyuki Ochi,et al. Breadth-first manipulation of SBDD of boolean functions for vector processing , 1991, 28th ACM/IEEE Design Automation Conference.
[19] Alexander Saldanha,et al. Fast discrete function evaluation using decision diagrams , 1995, ICCAD.
[20] Rolf Drechsler,et al. Augmented sifting of multiple-valued decision diagrams , 2003, 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings..
[21] Richard Rudell. Dynamic variable ordering for ordered binary decision diagrams , 1993, ICCAD.
[22] Shinobu Nagayama,et al. Representations of logic functions using QRMDDs , 2002, Proceedings 32nd IEEE International Symposium on Multiple-Valued Logic.
[23] H. T. Kung,et al. The Area-Time Complexity of Binary Multiplication , 1981, JACM.
[24] D. Michael Miller. Multiple-valued logic design tools , 1993, [1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic.
[25] Masahiro Fujita,et al. On variable ordering of binary decision diagrams for the application of multi-level logic synthesis , 1991, Proceedings of the European Conference on Design Automation..
[26] Hiroshi Sawada,et al. Minimization of binary decision diagrams based on exchanges of variables , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[27] Jonathan Rose,et al. Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency , 1990 .
[28] Nagisa Ishiura,et al. Shared binary decision diagram with attributed edges for efficient Boolean function manipulation , 1990, 27th ACM/IEEE Design Automation Conference.
[29] Hiroyuki Ochi,et al. Breadth-first manipulation of very large binary-decision diagrams , 1993, ICCAD.
[30] I. Wegener. Branching Programs and Binary Deci-sion Diagrams-Theory and Applications , 1987 .
[31] Tsutomu Sasao,et al. Heuristics to Minimize Multiple-Valued Decision Diagrams , 2000 .
[32] Chen-Shang Lin,et al. On the OBDD-Representation of General Boolean Functions , 1992, IEEE Trans. Computers.
[33] Ingo Wegener,et al. Branching Programs and Binary Decision Diagrams , 1987 .
[34] Steven J. E. Wilton,et al. On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques , 2002, FPGA '02.