Read/write margin enhanced 10T SRAM for low voltage application

[1]  Anna W. Topol,et al.  Stable SRAM cell design for the 32 nm node and beyond , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[2]  Hong Zhu,et al.  A Comprehensive Comparison of Data Stability Enhancement Techniques With Novel Nanoscale SRAM Cells Under Parameter Fluctuations , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Sied Mehdi Fakhraie,et al.  A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Kaushik Roy,et al.  A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  N. Vallepalli,et al.  A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply , 2005, IEEE Journal of Solid-State Circuits.

[6]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[7]  Yeonbae Chung,et al.  Differential-read symmetrical 8T SRAM bit-cell with enhanced data stability , 2010 .

[8]  David Blaauw,et al.  Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

[9]  Meng-Fan Chang,et al.  A Differential Data-Aware Power-Supplied (D$^{2}$AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications , 2009, IEEE Journal of Solid-State Circuits.

[10]  Mohammad Sharifkhani,et al.  A Subthreshold Symmetric SRAM Cell With High Read Stability , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[11]  Farshad Moradi,et al.  A new write assist technique for SRAM design in 65 nm CMOS technology , 2015, Integr..

[12]  Yong Li,et al.  Single-ended, robust 8T SRAM cell for low-voltage operation , 2013, Microelectron. J..

[13]  Jaspal Singh Shah,et al.  A 32 kb Macro with 8T Soft Error Robust, SRAM Cell in 65-nm CMOS , 2015, IEEE Transactions on Nuclear Science.

[14]  Naveen Verma,et al.  Ultra Low Voltage SRAM Design , 2009 .

[15]  C. B. Kushwah,et al.  A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.