FPGA implementation of a HW/SW platform for multimedia embedded systems

This paper presents a HW/SW platform for embedded video system. It has been designed around an embedded RISC processor and FPGA technologies and provides video input and output interfaces. The configurable platform has been used to implement a real time video processing and vision systems. The Altera’s Nios II development board was chosen to realise this real time video platform which uses μClinux as embedded Linux Operating System. Experimental results using H.263 video encoder show that this platform provides enough resources and speed to implement even complex multimedia embedded systems in real time.

[1]  N. Ahmed,et al.  Discrete Cosine Transform , 1996 .

[2]  Avideh Zakhor,et al.  Performance analysis of an H.263 video encoder for VIRAM , 2000, Proceedings 2000 International Conference on Image Processing (Cat. No.00CH37101).

[3]  Faouzi Kossentini,et al.  H.263+: video coding at low bit rates , 1998, IEEE Trans. Circuits Syst. Video Technol..

[4]  Nam Ik Cho,et al.  A fast 4×4 DCT algorithm for the recursive 2-D DCT , 1992, IEEE Trans. Signal Process..

[5]  Stephan Wong,et al.  Alternatives in FPGA-based SAD implementations , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

[6]  Jo Yew Tham,et al.  A novel unrestricted center-biased diamond search algorithm for block motion estimation , 1998, IEEE Trans. Circuits Syst. Video Technol..

[7]  G.S. Moschytz,et al.  Practical fast 1-D DCT algorithms with 11 multiplications , 1989, International Conference on Acoustics, Speech, and Signal Processing,.

[8]  Hsueh-Ming Hang,et al.  Real-time implementation of H.263+ using TI TMS320c6201 digital signal processor , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[9]  Anil K. Jain,et al.  Displacement Measurement and Its Application in Interframe Image Coding , 1981, IEEE Trans. Commun..

[10]  Ahmed Ben Atitallah,et al.  Optimization and Implementation on Fpga of the DCT/IDCT Algorithm , 2006, 2006 IEEE International Conference on Acoustics Speech and Signal Processing Proceedings.

[11]  Ishfaq Ahmad,et al.  Optimization of H.263 video encoding using a single processor computer: performance tradeoffs and benchmarking , 2001, IEEE Trans. Circuits Syst. Video Technol..

[12]  Kuei-Ann Wen,et al.  On the design of selective coefficient DCT module , 1998, IEEE Trans. Circuits Syst. Video Technol..

[13]  Ieee Standards Board,et al.  IEEE standard specifications for the implementations of 8x8 inverse discrete cosine transform , 1991 .

[14]  Peter Pirsch,et al.  VLSI architectures for video compression-a survey , 1995, Proc. IEEE.

[15]  Yuk-Hee Chan,et al.  A cyclic correlated structure for the realization of discrete cosine transform , 1992 .

[16]  K. Rijkse,et al.  H.263: video coding for low-bit-rate communication , 1996, IEEE Commun. Mag..

[17]  Kaj Fagervik,et al.  Optimization of an , 1999 .

[18]  Keun-Bae Kim,et al.  Modular and efficient architecture for H.263 video codec VLSI , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[19]  Lurng-Kuo Liu,et al.  A block-based gradient descent search algorithm for block motion estimation in video coding , 1996, IEEE Trans. Circuits Syst. Video Technol..

[20]  Lap-Pui Chau,et al.  Hexagon-based search pattern for fast block motion estimation , 2002, IEEE Trans. Circuits Syst. Video Technol..