HySim: A fast simulation framework for embedded software development

Instruction Set Simulation (ISS) is widely used in system evaluation and software development for embedded processors. Despite the significant advancements in the ISS technology, it still suffers from low simulation speed compared to real hardware. Especially for embedded software developers simulation speed close to real time is important in order to efficiently develop complex software. In this paper a novel, retargetable, hybrid simulation framework (HySim) is presented which allows switching between native code execution and ISS-based simulation. To reach a certain state of an application as fast as possible, all platform-independent parts of the application are directly executed on the host, while the platform dependent code executes on the ISS. During the native code execution a performance estimation is conducted. A case study shows that speed-ups ranging from 7× to 72× can be achieved without compromising debugging accuracy. The performance estimation during native code execution shows an average error of 9.5%.

[1]  David J. Lilja,et al.  Simulation of computer architectures: simulators, benchmarks, methodologies, and recommendations , 2006, IEEE Transactions on Computers.

[2]  Brad Calder,et al.  Automatically characterizing large scale program behavior , 2002, ASPLOS X.

[3]  Lei Gao,et al.  A fast and generic hybrid simulation approach using C virtual machine , 2007, CASES '07.

[4]  Brian W. Kernighan,et al.  The C Programming Language , 1978 .

[5]  Jianwen Zhu,et al.  DynamoSim: a trace-based dynamically compiled instruction set simulator , 2004, ICCAD 2004.

[6]  Kingshuk Karuri,et al.  Fine-grained application source code profiling for ASIP design , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[7]  Peter K. Szwed,et al.  SimSnap: fast-forwarding via native execution and application-level checkpointing , 2004, Eighth Workshop on Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004..

[8]  Alfred V. Aho,et al.  Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.

[9]  Roland E. Wunderlich,et al.  SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling , 2003, 30th Annual International Symposium on Computer Architecture, 2003. Proceedings..

[10]  Ahmed Amine Jerraya,et al.  Programming models and HW-SW interfaces abstraction for multi-processor SoC , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[11]  Kingshuk Karuri,et al.  A SW performance estimation framework for early system-level-design using fine-grained instrumentation , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[12]  Alfred V. Aho,et al.  Compilers: Principles, Techniques, and Tools (2nd Edition) , 2006 .

[13]  Daniel Marques,et al.  Collective operations in application-level fault-tolerant MPI , 2003, ICS '03.

[14]  Trevor N. Mudge,et al.  Intrinsic Checkpointing: A Methodology for Decreasing Simulation Time Through Binary Modification , 2005, IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005..

[15]  G. Braun,et al.  A universal technique for fast and flexible instruction-set architecture simulation , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[16]  Ahmed Amine Jerraya,et al.  Building fast and accurate SW simulation models based on hardware abstraction layer and simulation environment abstraction layer , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[17]  Daniel Marques,et al.  Automated application-level checkpointing of MPI programs , 2003, PPoPP '03.

[18]  Brad Calder,et al.  Discovering and Exploiting Program Phases , 2003, IEEE Micro.

[19]  Bjarne Stroustrup,et al.  The C++ programming language (2nd ed.) , 1991 .

[20]  Nikil D. Dutt,et al.  Instruction set compiled simulation: a technique for fast and flexible instruction set simulation , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[21]  IEEE standard for binary floating-point arithmetic - IEEE standard 754-1985 , 1985 .

[22]  Xinping Zhu,et al.  A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).