A disturb-free subthreshold 9T SRAM cell with improved performance and variation tolerance

This paper presents a novel subthreshold 9T SRAM cell with row-based Word-Line (WL) and column-based data-aware Write Word-Lines (WWLs). The decoupled Read port and cross-point Write structure provide a disturb-free cell and facilitate bit-interleaving architecture to improve soft error immunity. Compared with a previous cross-point Write 9T subthreshold SRAM cell reported in the literature, the proposed 9T SRAM cell offers comparable stability with improved Read performance and variation-tolerance. Monte Carlo simulations based on UMC 40nm Low-Power (40LP) technology indicate that the BL access time improves by 15.35% to 17.37%, and the variation (τ of BL access time) improves by 5.12% to 9.22% for VDD ranging from 0.3V to 0.6V. Based on a 72Kb SRAM macro design in UMC 40LP process, the proposed 9T cell achieves about 9% better chip access time (Ta) at SS corner for VDD ranging from 0.3V to 0.45V.

[1]  A.P. Chandrakasan,et al.  A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[2]  A.P. Chandrakasan,et al.  A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy , 2008, IEEE Journal of Solid-State Circuits.

[3]  Kevin G. Stawiasz,et al.  A 512kb 8T SRAM Macro Operating Down to 0.57 V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm SOI CMOS , 2011, IEEE Journal of Solid-State Circuits.

[4]  Rajiv V. Joshi,et al.  A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Chien-Yu Lu,et al.  A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing , 2012, IEEE Journal of Solid-State Circuits.

[6]  Sanghyeon Baeg,et al.  SRAM Interleaving Distance Selection With a Soft Error Failure Model , 2009, IEEE Transactions on Nuclear Science.

[7]  R.H. Dennard,et al.  An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches , 2008, IEEE Journal of Solid-State Circuits.

[8]  Nii Koji,et al.  A 45nm 0.6V Cross-Point 8T SRAM with Negative Biased Read/Write Assist , 2010 .

[9]  Meng-Fan Chang,et al.  A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications , 2011, IEEE Journal of Solid-State Circuits.

[10]  Masanori Hashimoto,et al.  Alpha-particle-induced soft errors and multiple cell upsets in 65-nm 10T subthreshold SRAM , 2010, 2010 IEEE International Reliability Physics Symposium.

[11]  Meng-Fan Chang,et al.  A Large $\sigma $V$_{\rm TH}$/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme , 2011, IEEE Journal of Solid-State Circuits.

[12]  Shi-Yu Huang,et al.  P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation , 2011, IEEE Journal of Solid-State Circuits.

[13]  C.H. Kim,et al.  A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V$_{\min}$ Lowering Techniques and Deep Sleep Mode , 2008, IEEE Journal of Solid-State Circuits.

[14]  Alexander Fish,et al.  A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM) , 2011, IEEE Journal of Solid-State Circuits.

[15]  Ching-Te Chuang,et al.  High-performance SRAM in nanoscale CMOS: Design challenges and techniques , 2007, 2007 IEEE International Workshop on Memory Technology, Design and Testing.

[16]  Ming-Chien Tsai,et al.  Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  H. Yamauchi,et al.  A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses , 2008, IEEE Journal of Solid-State Circuits.

[18]  Kaushik Roy,et al.  A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[19]  Jan M. Rabaey,et al.  Ultralow-Power Design in Near-Threshold Region , 2010, Proceedings of the IEEE.