System level design and debug of high-performance embedded media systems (embedded tutorial)

This tutorial on System Level Design practices in Philips consists of three parts. In the first part we discuss application domain characteristics and architectures for video processing. High performance video processing applications impose severe demands on architectures. The architectures need to provide both high bandwidth for communication and high processing power for computation. Such architectures often consist of a combination of programmable cores and more dedicated coprocessors. This is illustrated with the TriMedia based VLIW cores combined with dedicated coprocessors, e.g., an HD resolution MPEG-2 decoder and a dedicated video output processing unit. Several architectures that are developed within Philips will be illustrated. These include the programmable TriMedia VLIW media processor, a dataflow style stream processing architecture, and more dedicated solutions for video processing. Furthermore the future trend of building platforms out of these components will be illustrated. In the second part we discuss the design technology that is employed to perform architecture modeling and evaluation and design space exploration. During the initial stages of architecture design several decisions with a large impact are taken. In Philips, practice is developed to model architectures at a high level of abstraction. With such models architectural options can be explored quantitatively. Such explorations are driven by a suite of characteristic benchmark applications. Several levels of architecture modeling will be illustrated. Methods and tools used for exploration ob both a multiprocessor system including a dedicated MPEG-2 decoder and a future VLIW core will be presented. In the third part we discuss a methodology for System-On-a-Chip debug. For today's multi-million transistor designs, existing design verification techniques cannot guarantee that first silicon is designed error free. Therefore, techniques are necessary to quickly debug first-silicon. In this presentation, we present a methodology for debugging multiple clock domain systems-on-a-chip. The methodology supports the insertion of special debug components in the design (Design-for-Debug). After silicon becomes available debugger tool software is used to interact with these components to enable silicon debugging from a workstation. The tool software provided features such as the ones commonly found in simulation environments e.g., breakpoints and virtual probles. The application of these techniques to a dataflow style video processor will be illustrated.