Maintaining a reliable low-power self-refresh state of the memory circuit

The invention provides a low power consumption circuit for reliably keeping a self-refresh state of a memory. The low power consumption circuit comprises a first resistor, a second resistor and a plug and play (PNP) triode, wherein a base of the PNP triode is connected with one end of the first resistor and an output end of a memory controller respectively, and the other end of the first resistoris grounded; an emitter of the PNP triode is connected with one end of the second resistor and an input end of a clock signal of the memory respectively, and the other end of the second resistor is grounded; and a collector of the PNP triode is grounded. By the circuit, the memory can be stably and reliably kept in the self-refresh state; and the circuit is not required to be additionally supplied with power.