Manufacturing of 3-D Packaged Systems

This chapter describes the concepts of vertical integration and system-on-package (SoP), and the commonality between these paradigms. It focuses on several three-dimensional (3-D) technologies for 3-D packaging and describes the cost models related to these technologies. It summarizes the technological implications of 3-D integration at the package level. One of the first initiatives demonstrating 3-D circuits was reported in 1981. This work involved the vertical integration of PMOS and NMOS devices with a single gate to create an inverter, considerably reducing the total area and capacitance of the inverter. Several other approaches to 3-D integration have been developed, both at the package and circuit levels. Bare or packaged die is vertically integrated, permitting a broad variety of interconnection strategies. Each of these vertical interconnection techniques has different advantages and disadvantages. Die or package bonding can be implemented by utilizing a diverse collection of materials, such as epoxy and other polymers. A system-in-package (SiP) constitutes a significant and widely commercialized variant of vertical integration. The driving force toward SiP is the increase in packaging efficiency, which is characterized by the die-to-package area ratio, the reduced package footprint, and the decreased weight. Homogeneous systems consisting of multiple memory dies and heterogeneous stacks including combinations of memory modules and an ASIC or a microprocessor are the most common type of SiP and have been commercialized by several companies.