A 7GS/s direct digital frequency synthesizer with a two-times interleaved RDAC in 65nm CMOS

A 7GS/s DDFS MMIC featuring a Two-Times Interleaved RDAC with 1.2Vpp-diff output swing was fabricated in 65nm CMOS. The frequency tuning and amplitude resolutions are 24-bits and 10-bits respectively. The RDAC includes a mixed-signal, high-speed architecture for Random Swapping Thermometer Coding Dynamic Element Matching that improves the narrowband SFDR up to 8dB for output frequencies below 1.85GHz. The worst case wideband/narrowband SFDR is 32dBc/42dBc. This system consumes 87.9mW/(GS/s) from a 1.2V power supply when the RSTC-DEM method is enabled, resulting in a FoM of 458.9GS/s-2(SFDR/6)/W. A Proof-of-Concept chip with an active area of only 0.22mm2 was measured in LQFP packages.

[1]  Foster F. Dai,et al.  24-Bit 5.0 GHz Direct Digital Synthesizer RFIC With Direct Digital Modulations in 0.13 $\mu$ m SiGe BiCMOS Technology , 2010, IEEE Journal of Solid-State Circuits.

[2]  Anne-Johan Annema,et al.  An Interleaved Full Nyquist High-Speed DAC Technique , 2015, IEEE Journal of Solid-State Circuits.

[3]  Foster F. Dai,et al.  An 11-Bit 8.6 GHz Direct Digital Synthesizer MMIC With 10-Bit Segmented Sine-Weighted DAC , 2010, IEEE Journal of Solid-State Circuits.

[4]  S.E. Turner,et al.  ROM-Based Direct Digital Synthesizer at 24 GHz Clock Frequency in InP DHBT Technology , 2008, IEEE Microwave and Wireless Components Letters.

[5]  Ching-Yuan Yang,et al.  A 5-GHz Direct Digital Frequency Synthesizer Using an Analog-Sine-Mapping Technique in 0.35- $\mu$m SiGe BiCMOS , 2011, IEEE Journal of Solid-State Circuits.

[6]  Akira Matsuzawa,et al.  A 10-bit 6.8-GS/s Direct Digital Frequency Synthesizer Employing Complementary Dual-Phase Latch-Based Architecture , 2016, IEICE Trans. Electron..

[7]  Po-Chiun Huang,et al.  A 14-bit 200MS/s current-steering DAC achieving over 82dB SFDR with digitally-assisted calibration and dynamic matching techniques , 2012, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test.

[8]  Po-Chiun Huang,et al.  Random Swapping Dynamic Element Matching Technique for Glitch Energy Minimization in Current-Steering DAC , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[9]  S.E. Turner,et al.  Direct Digital Synthesizer With Sine-Weighted DAC at 32-GHz Clock Frequency in InP DHBT Technology , 2006, IEEE Journal of Solid-State Circuits.

[10]  Sung-Mo Kang,et al.  A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS , 2014, IEEE Journal of Solid-State Circuits.