DESIGN OF A RISC MICROCONTROLLER CORE IN 48 HOURS

In this paper we present a design case study using Handel-C — a recently developed programming language for compilation of high-level programs directly into FPGA hardware. The design is an 8-bit RISC microcontroller core with 33 instructions, prescaler and a programmable timer. Handel-C was used throughout the entire design and debugging flow. The RISC microcontroller d esign was implementedon the XESS XS40 FPGA boardwith Xilinx XC4010XL FPGA. The overall d esign, including debugging, testing and the FPGA implementation was completed in less than 48 man-hours. K e y w o r d s: Handel-C, RISC architecture, design methodology, FPGA, design flow Increasing performance and gate capacity of recent FPGA devices permits complex logic systems to be implemented on a single programmable device. Such a growing complexity demands design approaches, which can cope with designs containing hundreds of thousands of logic gates, memories, high-speed interfaces, and other highperformance components. One category of such design approaches are design methodologies based on languages derived from traditional programming languages such as C, Pascal, Java or others. These allow designers to use the familiar language syntax to develop hardware systems at high level. In this paper we present a design case study of a RISC microcontroller core, designed using a hardware compilation design flow. A C-like language called HandelC is used for the hardware design. The goal of this work was to evaluate the feasibility of using Handel-C for rapid design and prototyping of microprocessors. In the following Section 2 we outline the architecture of the RISC microcontroller implemented in this design case study. Section 3 details the implementation methodology, including some real examples of Handel-C code used in the design and the overall project details. The paper concludes with a summary in Section 4.