X-canceling MISR — An X-tolerant methodology for compacting output responses with unknowns using a MISR

A new X-tolerant multiple-input signature register (MISR) compaction methodology is proposed which can compact output streams containing unknown (X) values. Unlike conventional X-masking approaches, it does not require any masking logic at the input of the MISR. Instead it uses symbolic simulation to express each bit of the MISR signature as a linear equation in terms of the X's. Linearly dependent combinations of the signature bits are identified with Gaussian elimination and XORed together using a programmable XOR to cancel out all X values thereby yielding deterministic values that are invariant of what the final values of the X's end up being during the test. These X-canceled values can be compacted in a separate MISR to generate a final X-free signature. Each intermediate signature for an m-bit MISR can tolerate k X's present anywhere in the output stream with error detection capability equivalent to using an m-k bit MISR with no unknowns. The tester storage requirement is a small constant times the total number of unknowns in the test set and thus does not depend on the scan architecture, the number of test vectors, or the distribution of X's which is a key advantage compared with other X-tolerant compaction schemes.

[1]  Janak H. Patel,et al.  Application of Saluja-Karpovsky compactors to test responses with many unknowns , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[2]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[3]  Vivek Chickermane,et al.  Channel masking synthesis for efficient on-chip test compression , 2004, 2004 International Conferce on Test.

[4]  Steven S. Lumetta,et al.  X-tolerant signature analysis , 2004 .

[5]  Nilanjan Mukherjee,et al.  X-Press Compactor for 1000x Reduction of Test Data , 2006, 2006 IEEE International Test Conference.

[6]  Irith Pomeranz,et al.  On output response compression in the presence of unknown output values , 2002, DAC '02.

[7]  Sudhakar M. Reddy,et al.  Finite memory test response compactors for embedded test applications , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Peter Wohl,et al.  Scalable selector architecture for X-tolerant deterministic BIST , 2004, Proceedings. 41st Design Automation Conference, 2004..

[9]  Brion L. Keller,et al.  OPMISR: the foundation for compressed ATPG vectors , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[10]  Mark G. Karpovsky,et al.  Testing Computer Hardware through Data Compression in Space and Time , 1983, ITC.

[11]  Minesh B. Amin,et al.  X-tolerant compression and application of scan-atpg patterns in a bist architecture , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[12]  Wu-Tung Cheng,et al.  X-filter: filtering unknowns from compacted test responses , 2005, IEEE International Conference on Test, 2005..

[13]  Vivek Chickermane,et al.  Channel masking synthesis for efficient on-chip test compression , 2004 .

[14]  John W. Auer,et al.  Linear algebra with applications , 1996 .

[15]  Janusz Rajski,et al.  Automated synthesis of phase shifters for built-in self-testapplications , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Erik H. Volkerink,et al.  Response compaction with any number of unknowns using a new LFSR architecture , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[17]  Kwang-Ting Cheng,et al.  Response shaper: a novel technique to enhance unknown tolerance for output response compaction , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[18]  Xiaoqing Wen,et al.  VLSI Test Principles and Architectures , 2006 .

[19]  Subhasish Mitra,et al.  X-compact: an efficient response compaction technique , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Thomas W. Williams,et al.  Design of compactors for signature-analyzers in built-in self-test , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[21]  Charles G. Cullen.  Linear algebra with applications , 1988 .

[22]  Bernd Becker,et al.  X-masking during logic BIST and its impact on defect coverage , 2006, IEEE Trans. Very Large Scale Integr. Syst..

[23]  Janusz Rajski,et al.  Modular compactor of test responses , 2006, 24th IEEE VLSI Test Symposium.