On the nonenumerative path delay fault simulation problem
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[1] Spyros Tragoudas,et al. ATPG for path delay faults without path enumeration , 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.
[2] Kwang-Ting Cheng,et al. Delay testing for non-robust untestable circuits , 1993, Proceedings of IEEE International Test Conference - (ITC).
[3] Spyros Tragoudas,et al. Exact path delay grading with fundamental BDD operations , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[4] Spyros Tragoudas,et al. ATPD: an automatic test pattern generator for path delay faults , 1996, Proceedings International Test Conference 1996. Test and Design Validity.
[5] Janak H. Patel,et al. Improving a nonenumerative method to estimate path delay fault coverage , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[6] B. Kapoor. An efficient method for computing exact path delay fault coverage , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.
[7] Vishwani D. Agrawal,et al. An exact non-enumerative fault simulator for path-delay faults , 1996, Proceedings International Test Conference 1996. Test and Design Validity.
[8] Michael Pabst,et al. RESIST: a recursive test pattern generation algorithm for path delay faults , 1994, EURO-DAC '94.
[9] Michael H. Schulz,et al. Parallel Pattern Fault Simulation of Path Delay Faults , 1989, 26th ACM/IEEE Design Automation Conference.
[10] Irith Pomeranz,et al. An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[11] Spyros Tragoudas. Accurate path delay fault coverage is feasible , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).
[12] Melvin A. Breuer,et al. Digital systems testing and testable design , 1990 .
[13] David S. Johnson,et al. Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .
[14] Janak H. Patel,et al. Improving accuracy in path delay fault coverage estimation , 1996, Proceedings of 9th International Conference on VLSI Design.
[15] Irith Pomeranz,et al. NEST: a nonenumerative test generation method for path delay faults in combinational circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[16] S. Tragoudas,et al. Maximum independent sets on transitive graphs and their applications in testing and CAD , 1997, ICCAD 1997.
[17] Vishwani D. Agrawal,et al. An Efficient Path Delay Fault Coverage Estimator , 1994, 31st Design Automation Conference.
[18] Spyros Tragoudas,et al. Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[19] Spyros Tragoudas,et al. Color counting and its application to path delay fault coverage , 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.
[20] Irith Pomeranz,et al. A method for identifying robust dependent and functionally unsensitizable paths , 1997, Proceedings Tenth International Conference on VLSI Design.
[21] Janak H. Patel,et al. Segment delay faults: a new fault model , 1996, Proceedings of 14th VLSI Test Symposium.