论文信息 - A fast parallel multiplier architecture

A fast parallel multiplier architecture

A parallel multiplier architecture is presented that is both fast and small and a viable alternative to the array and tree type multipliers. The speed of this architecture is close to that of the binary and Wallace tree architectures for common sizes of multipliers, while the area is only marginally larger than that of the array multiplier. The structure of the architecture is very regular, making it ideal for automatic generation. The internal structure of this floorplan can be generated very easily from a set of seven VLSI leafcells requiring no extra routing.<<ETX>>

R. Nouta | G. J. Hekstra | R. Nouta | G. Hekstra

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