High-Speed Hybrid Parallel-Prefix Carry-Select Adder Using Ling's Algorithm

Parallel-prefix adders offer high efficiency solution in terms of area, speed, power and regularity to the binary addition problem and are well suited for VLSI implementation. In this paper, a novel technique of implementing a hybrid parallel- prefix ling adder is presented. Experimental results show that the proposed adder has an improvement of 63% in speed and about 13% reduction in power consumption compared to Carry Lookahead adder (CLA).

[1]  Israel Koren.  Computer arithmetic algorithms , 1993 .

[2]  Simon Knowles,et al.  A family of adders , 1999, Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336).

[3]  Sanu Mathew,et al.  Comparison of high-performance VLSI adders in the energy-delay space , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Harold S. Stone,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.

[5]  Tack-Don Han,et al.  Fast area-efficient VLSI adders , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).

[6]  Jack Sklansky,et al.  Conditional-Sum Addition Logic , 1960, IRE Trans. Electron. Comput..

[7]  Robert W. Doran.  Variants of an Improved Carry Look-Ahead Adder , 1988, IEEE Trans. Computers.

[8]  Huey Ling.  High Speed Binary Adder , 1981, IBM J. Res. Dev..

[9]  Stamatis Vassiliadis.  Recursive equations for hardwired binary adders , 1989 .

[10]  H. T. Kung,et al.  A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.

[11]  Yuke Wang,et al.  The design of hybrid carry-lookahead/carry-select adders , 2002 .