论文信息 - Layout impact of resolution enhancement techniques: impediment or opportunity?

Layout impact of resolution enhancement techniques: impediment or opportunity?

This tutorial introduces the reader to the basic concepts of optical lithography, derives fundamental resolution limits, reviews the challenges facing future technology nodes, explains the principles of resolution enhancement techniques and their impact on chip layout, and discusses layout optimization considerations.

Lars Liebmann | L. Liebmann

[1] Lars W. Liebmann,et al. Layout optimization at the pinnacle of optical lithography , 2003, SPIE Advanced Lithography.

[2] Fook-Luen Heng,et al. Enabling alternating phase shifted mask designs for a full logic gate level , 2002 .

[3] Lars W. Liebmann,et al. Optimizing style options for subresolution assist features , 2001, SPIE Advanced Lithography.

[4] Fook-Luen Heng,et al. Enabling alternating phase shifted mask designs for a full logic gate level: design rules and design rule checking , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[5] Franklin M. Schellenberg,et al. Model-assisted double dipole decomposition , 2002, SPIE Advanced Lithography.

[6] Lars W. Liebmann,et al. Lithographic comparison of assist feature design strategies , 2000, Advanced Lithography.

[7] Fook-Luen Heng,et al. Enabling the 70nm technology node with 193nm altPSM lithography , 2002 .

[8] 山下茂. 39th Design Automation Conference , 2002 .

[9] Burn Jeng Lin. Semiconductor foundry, lithography, and partners , 2002, SPIE Advanced Lithography.