Diagnosis of interconnect shorts in mesh NoCs

We propose a method to diagnose interconnect short-circuit faults in mesh 7oCs. The fault model comprises all shorts between any two wires of a defined 7oC neighborhood. Test sequences are applied in 7oC functional mode. Experimental results show that 93% of the interconnect shorts can be diagnosed.

[1]  Partha Pratim Pande,et al.  On-line fault detection and location for NoC interconnects , 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

[2]  William H. Kautz,et al.  Testing for Faults in Wiring Networks , 1974, IEEE Transactions on Computers.

[3]  Partha Pratim Pande,et al.  BIST for network-on-chip interconnect infrastructures , 2006, 24th IEEE VLSI Test Symposium.

[4]  Jong-Sun Kim,et al.  On-chip network based embedded core testing , 2004, IEEE International SOC Conference, 2004. Proceedings..

[5]  Alexandre M. Amory,et al.  A scalable test strategy for network-on-chip routers , 2005, IEEE International Conference on Test, 2005..

[6]  Raimund Ubar,et al.  Test Configurations for Diagnosing Faulty Links in NoC Switches , 2007, 12th IEEE European Test Symposium (ETS'07).

[7]  Altamiro Amadeu Susin,et al.  SoCIN: a parametric and scalable network-on-chip , 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

[8]  Alexandre M. Amory,et al.  A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip , 2008, IEEE Transactions on Computers.

[9]  Radu Marculescu,et al.  DyAD - smart routing for networks-on-chip , 2004, Proceedings. 41st Design Automation Conference, 2004..

[10]  Melvin A. Breuer,et al.  MAXIMAL DIAGNOSIS FOR WIRING NETWORKS , 1991, 1991, Proceedings. International Test Conference.

[11]  Spyros Tragoudas,et al.  Interconnect testing for networks on chips , 2006, 24th IEEE VLSI Test Symposium.

[12]  Kees G. W. Goossens,et al.  Bringing communication networks on a chip: test and verification implications , 2003, IEEE Commun. Mag..

[13]  Vinod K. Agarwal,et al.  Testing and diagnosis of interconnects using boundary scan architecture , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[14]  Partha Pratim Pande,et al.  Methodologies and algorithms for testing switch-based NoC interconnects , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[15]  R. Ubar,et al.  An External Test Approach for Network-on-a-Chip Switches , 2006, 2006 15th Asian Test Symposium.

[16]  Jin HoAhn,et al.  Test Scheduling of NoC-Based SoCs Using Multiple Test Clocks , 2006 .

[17]  Luigi Carro,et al.  Reusing an on-chip network for the test of core-based systems , 2004, TODE.