Verus: a tool for quantitative analysis of finite-state real-time systems

Symbolic model checking is a technique for verifying finite-state concurrent systems. Models with up to 1030 states can often be verified in minutes. In this paper, we present a new tool to analyze real-time systems, based on this technique. We have designed a language, called Verus, for the description of real-time systems. Such a description is compiled into a state-transition graph and represented symbolically using binary decision diagrams. We have developed new algorithms for exploring the state space and computing quantitative information about the system. In addition to determining the exact bounds on the length of the time interval between two specified events, we compute the number of occurrences of an event in such an interval. This technique allows us to determine performance measures such as schedulability, response time, and system load. Our algorithms produce more detailed information than traditional methods. This information leads to a better understanding of the behavior of the system, in addition to verifying if its timing requirements are satisfied. We integrate these ideas into the Verus tool, currently under development. To demonstrate how our technique works, we have verified a robotics control system. The results obtained demonstrate that our method can be successfully applied in the analysis of real-time system designs.

[1]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[2]  Kenneth L. McMillan,et al.  Symbolic model checking: an approach to the state explosion problem , 1992 .

[3]  Sérgio Vale Aguiar Campos,et al.  Computing quantitative characteristics of finite-state real-time systems , 1994, 1994 Proceedings Real-Time Systems Symposium.

[4]  Rance Cleaveland,et al.  RTSL: a language for real-time schedulability analysis , 1993, 1993 Proceedings Real-Time Systems Symposium.

[5]  Farn Wang,et al.  Symbolic model checking for event-driven real-time systems , 1993, 1993 Proceedings Real-Time Systems Symposium.

[6]  A. Prasad Sistla,et al.  Quantitative Temporal Reasoning , 1990, CAV.

[7]  Ragunathan Rajkumar Task synchronization in real-time systems , 1989 .

[8]  Edmund M. Clarke,et al.  Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic , 1981, Logic of Programs.

[9]  I. Lee,et al.  A proof system for communicating shared resources , 1990, [1990] Proceedings 11th Real-Time Systems Symposium.

[10]  Lui Sha,et al.  Rate Monotonic Analysis for Real-Time Systems , 1991 .

[11]  Somesh Jha,et al.  Verification of the Futurebus+ cache coherence protocol , 1993, Formal Methods Syst. Des..

[12]  Edmund M. Clarke,et al.  Symbolic Model Checking: 10^20 States and Beyond , 1990, Inf. Comput..

[13]  John P. Lehoczky,et al.  Timing Analysis for Fixed-Priority Scheduling of Hard Real-Time Systems , 1994, IEEE Trans. Software Eng..