VLSI circuit partitioning by cluster-removal using iterative improvement techniques

Move-based iterative improvement partitioning methods such as the Fiduccia-Mattheyses (FM) algorithm and Krishnamurthy's Look-Ahead (LA) algorithm are widely used in VLSI CAD applications largely due to their time efficiency and ease of implementation. This class of algorithms is of the "local improvement" type. They generate relatively high quality results for small and medium size circuits. However, as VLSI circuits become larger, these algorithms are not so effective on them as direct partitioning tools. We propose new iterative-improvement methods that select cells to move with a view to moving clusters that straddle the two subsets of a partition into one of the subsets. The new algorithms significantly improve partition quality while preserving the advantage of time efficiency. Experimental results on 25 medium to large size ACM/SIGDA benchmark circuits show up to 70% improvement over FM in cutsize, with an average of per-circuit percent improvements of about 25%, and a total cut improvement of about 35%. They also outperform the recent placement-based partitioning tool Paraboli and the spectral partitioner MELO by about 17% and 23%, respectively, with less CPU time. This demonstrates the potential of iterative improvement algorithms in dealing with the increasing complexity of modern VLSI circuitry.

[1]  Shantanu Dutt,et al.  Partitioning around roadblocks: tackling constraints with intermediate relaxations , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[2]  Chung-Kuan Cheng,et al.  Linear decomposition algorithm for VLSI design applications , 1995, ICCAD.

[3]  Konrad Doll,et al.  Partitioning Very Large Circuits Using Analytical Placement Techniques , 1994, 31st Design Automation Conference.

[4]  Shashi Shekhar,et al.  Multilevel hypergraph partitioning: application in VLSI domain , 1997, DAC.

[5]  Krzysztof Kozminski,et al.  Cost Minimization of Partitions into Multiple Devices , 1993, 30th ACM/IEEE Design Automation Conference.

[6]  Charles M. Fiduccia,et al.  A linear-time heuristic for improving network partitions , 1988, 25 years of DAC.

[7]  Malgorzata Marek-Sadowska.  Issues in Timing Driven Layout , 1993, Algorithmic Aspects of VLSI Layout.

[8]  Brian W. Kernighan,et al.  A proper model for the partitioning of electrical circuits , 1972, DAC '72.

[9]  Andrew B. Kahng,et al.  A hybrid multilevel/genetic approach for circuit partitioning , 1996, Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems.

[10]  Shantanu Dutt,et al.  A probability-based approach to VLSI circuit partitioning , 1996, DAC '96.

[11]  Chung-Kuan Cheng,et al.  An improved two-way partitioning algorithm with stable performance [VLSI] , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Malgorzata Marek-Sadowska,et al.  Timing driven placement , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[13]  Brian Kernighan,et al.  An efficient heuristic for partitioning graphs , 1970 .

[14]  Andrew B. Kahng,et al.  Fast spectral methods for ratio cut partitioning and clustering , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[15]  Gaetano Borriello,et al.  An evaluation of bipartitioning techniques , 1995, Proceedings Sixteenth Conference on Advanced Research in VLSI.

[16]  S. Dutt,et al.  A probability-based approach to VLSI circuit partitioning , 1996, 33rd Design Automation Conference Proceedings, 1996.

[17]  Shantanu Dutt,et al.  VLSI circuit partitioning by cluster-removal using iterative improvement techniques , 1996, ICCAD 1996.

[18]  Jason Cong,et al.  Large scale circuit partitioning with loose/stable net removal and signal flow based clustering , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[19]  Charles J. Alpert,et al.  Spectral Partitioning: The More Eigenvectors, The Better , 1995, 32nd Design Automation Conference.

[20]  R. M. Mattheyses,et al.  A Linear-Time Heuristic for Improving Network Partitions , 1982, 19th Design Automation Conference.

[21]  Andrew B. Kahng,et al.  A General Framework For Vertex Orderings, With Applications To Netlist Clustering , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[22]  Andrew B. Kahng,et al.  Multilevel circuit partitioning , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  Youssef Saab,et al.  A Fast and Robust Network Bisection Algorithm , 1995, IEEE Trans. Computers.

[24]  Balakrishnan Krishnamurthy,et al.  An Improved Min-Cut Algonthm for Partitioning VLSI Networks , 1984, IEEE Transactions on Computers.

[25]  Chung-Kuan Cheng,et al.  Towards efficient hierarchical designs by ratio cut partitioning , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[26]  Arvind Srinivasan,et al.  A fast algorithm for performance-driven placement , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[27]  S.,et al.  An Efficient Heuristic Procedure for Partitioning Graphs , 2022 .

[28]  S. Dutt.  New faster Kernighan-Lin-type graph-partitioning algorithms , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).