论文信息 - A 0 . 2 V 0 . 44 μ W 20 kHz Analog to Digital Modulator with 57 fJ / conversion FoM

A 0 . 2 V 0 . 44 μ W 20 kHz Analog to Digital Modulator with 57 fJ / conversion FoM

This paper presents a 90 nm CMOS Σ∆ A/D modulator operating with a supply voltage of 0.2V, well below the threshold voltage of the transistors. The modulator is an open-loop first-order architecture based on a frequencymodulated intermediate signal, generated in a ring voltagecontrolled oscillator. The linearity of the modulator is greatly improved by the adoption of a so-called soft-rail in the oscillator. Measurements show a dynamic range of 52 dB over a 20 kHz signal bandwidth with a sampling frequency of 3.4MHz, for a total power consumption as low as 0.44μW. The corresponding peak SNDR is 44.2 dB, while the peak SNR is 47.4 dB.

Wismar | Ulrik Sørensen

[1] M. Høvin,et al. Delta-sigma modulators using frequency-modulated intermediate values , 1997, IEEE J. Solid State Circuits.

[2] W. Fichtner,et al. MOS modelling by analytical approximations. I. Subthreshold current and threshold voltage , 1979 .

[3] M. Jamal Deen,et al. Performance characteristics of an ultra-low power VCO , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[4] U. Wismar,et al. Linearity of bulk-controlled inverter ring VCO in weak and strong inversion , 2007 .

[5] Peter R. Kinget,et al. 3.6 A 0.5V 74dB SNDR 25kHz CT ∆Σ Modulator with Return-to-Open DAC , 2006 .

[6] Yngvar Berg,et al. Real-time reconfigurable linear threshold elements implemented in floating-gate CMOS , 2003, IEEE Trans. Neural Networks.

[7] Michiel Steyaert,et al. Erratum to "A 1-V 140-μW 88-dB Audio Sigma-Delta Modulator in 90-nm CMOS" , 2009, IEEE J. Solid State Circuits.