Short-channel effects on the static noise margin of 6T SRAM composed of 2D semiconductor MOSFETs

This paper investigates the influence of the short-channel effects (SCEs) on the static noise margin (SNM) of 6T (6 transistors) SRAM composed of 2D MOSFETs. An analytical all-region I-V model for short-channel complementary 2D MOSFETs has been developed, and a simulation model has been built to calculate SNM with the consideration of SCEs and velocity saturation. The results show that there exists an optimal value of channel length (Lopt) where SNM reaches a maximum, and Lopt is approximately three times the scale length. In the region where L>Lopt, SNM increases slightly as L decreases because of velocity saturation, while in the region where L<Lopt, SNM decreases rapidly as L decreases as the SCEs are dominant. The worst case of SNM reduction due to the threshold voltage (VT) fluctuation is investigated, and the maximum VT tolerance is studied as a function of L. In an SRAM with a scale length of 5 nm, as L decreases from 15 nm to 5 nm, SNM decreases from 155 mV to 98 mV, and the maximum VT tolerance decreases from 126 mV to 105 mV.

[1]  Wei Wang,et al.  A continuous, analytic drain-current model for DG MOSFETs , 2004, IEEE Electron Device Letters.

[2]  Qian Xie,et al.  Investigation on the static noise margin of 6T SRAM composed of 2D semiconductor MOSFETs , 2016, 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

[3]  Yuan Taur,et al.  Static noise margin analysis of double-gate MOSFETs SRAM , 2009, 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

[4]  Yuan Taur,et al.  A 2-D analytical solution for SCEs in DG MOSFETs , 2004, IEEE Transactions on Electron Devices.

[5]  Zuochang Ye,et al.  An Efficient SRAM Yield Analysis and Optimization Method With Adaptive Online Surrogate Modeling , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Tao Yu,et al.  Impacts of short-channel effects on the random threshold voltage variation in nanoscale transistors , 2013, Science China Information Sciences.

[7]  Tian-Ling Ren,et al.  An analytical charge-sheet drain current model for monolayer transition metal dichalcogenide negative capacitance field-effect transistors , 2017, 2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM).

[8]  Yuan Taur,et al.  A Short-Channel $I$ – $V$ Model for 2-D MOSFETs , 2016 .

[9]  Kaustav Banerjee,et al.  A Compact Current–Voltage Model for 2D Semiconductor Based Field-Effect Transistors Considering Interface Traps, Mobility Degradation, and Inefficient Doping Effect , 2014, IEEE Transactions on Electron Devices.

[10]  P. D. Ye,et al.  $\hbox{MoS}_{2}$ Dual-Gate MOSFET With Atomic-Layer-Deposited $\hbox{Al}_{2}\hbox{O}_{3}$ as Top-Gate Dielectric , 2011, IEEE Electron Device Letters.

[11]  Yanqing Wu,et al.  Development of two-dimensional materials for electronic applications , 2016, Science China Information Sciences.

[12]  H. Beneking,et al.  Drift velocity saturation in MOS transistors , 1970 .

[13]  Yuan Taur,et al.  Review and Critique of Analytic Models of MOSFET Short-Channel Effects in Subthreshold , 2012, IEEE Transactions on Electron Devices.

[14]  Giuseppe Iannaccone,et al.  Electronics based on two-dimensional materials. , 2014, Nature nanotechnology.

[15]  David Jimenez,et al.  Drift-diffusion model for single layer transition metal dichalcogenide field-effect transistors , 2012 .

[16]  Lei Zhang,et al.  A Statistical Characterization of CMOS Process Fluctuations in Subthreshold Current Mirrors , 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

[17]  J. Lohstroh,et al.  Worst-case static noise margin criteria for logic circuits and their mathematical equivalence , 1983, IEEE Journal of Solid-State Circuits.

[18]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[19]  C. Hu,et al.  Field-effect transistors built from all two-dimensional material components. , 2014, ACS nano.

[20]  Han Liu,et al.  MoS 2 Dual-Gate MOSFET With Atomic-Layer-Deposited Al 2 O 3 as Top-Gate Dielectric , 2016 .