A low-power 10-Gb/s receiver with merged CTLE and DFE summer

This paper presents a wireline communication receiver with merged continuous-time linear equalizer (CTLE) and decision feedback equalizer (DFE) summer circuit. The merged circuit removes the traditional CTLE and merge it into the following DFE summer to builds linear equalization so as to significantly reduce the receiver power consumption. Analysis for the conventional equalizer and proposed circuit are presented. The proposed circuit architecture is experimentally verified at a 10 Gb/s wireline receiver with 0.45 mW/Gb/s power efficiency.

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