A novel clock generation algorithm for system-on-chip based on least common multiple

Display Omitted An algorithm to generate the clocks for the different cores in a System-on-Chip (SoC) is proposed.The algorithm minimizes the number of Phase Locked Loops (PLLs) required in a SoC.As a result, the power consumed by the clock generator circuit of a SoC can be reduced.Design cost and area of a SoC can also be minimized. Due to increase in the number of Intellectual Property (IP) cores, clock generation in current day System-on-Chips (SoCs) is facing a crisis. The conventional method of using a dedicated Phase Locked Loop (PLL) to generate the clock for each IP core is becoming inefficient in terms of power and cost. We propose an algorithm based on Least Common Multiple (LCM) to minimize the number of PLLs required to generate the clocks for the IP cores in a SoC. This is done by finding an Optimum Operating Frequency (OOF) for each IP core within 10% below the maximum operating frequency of the core. The OOF is chosen such that the LCM of the OOF of all the IP cores is minimized. Simulated annealing is used to find the LCM. This LCM is the crucial high frequency from which maximum number of clocks can be derived by clock dividers.

[1]  Axel Jantsch,et al.  Interconnect-Centric Design for Advanced SOC and NOC , 2010 .

[2]  Nadine Gottschalk,et al.  Vlsi Physical Design From Graph Partitioning To Timing Closure , 2016 .

[3]  Theo A. C. M. Claasen,et al.  An Industry Perspective on Current and Future State of the Art in System-on-Chip (SoC) Technology , 2006, Proceedings of the IEEE.

[4]  Stephan Henker,et al.  A novel ADPLL design using successive approximation frequency control , 2009, Microelectron. J..

[5]  Roberto Nonis,et al.  A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[6]  John Reuben,et al.  Low power, high speed hybrid clock divider circuit , 2013, 2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT).

[7]  Rochit Rajsuman.  System-On-A-Chip: Design and Test , 2000 .

[8]  Seongdo Kim,et al.  A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[10]  A.M. Fahim,et al.  Low-power direct digital frequency synthesis for wireless communications , 2000, IEEE Journal of Solid-State Circuits.

[11]  R. Engelbrecht,et al.  DIGEST of TECHNICAL PAPERS , 1959 .

[12]  Stephan Henzler,et al.  Design and Application of Power Optimized High-Speed CMOS Frequency Dividers , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Nasser A. Kurd,et al.  A multigigahertz clocking scheme for the Pentium(R) 4 microprocessor , 2001, IEEE J. Solid State Circuits.

[14]  Stephane Moins.  Implementation of a Simulated Annealing algorithm for Matlab , 2002 .

[15]  K. Nose,et al.  Deterministic inter-core synchronization with periodically all-in-phase clocking for low-power multi-core SoCs , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[16]  Liming Xiu.  Nanometer Frequency Synthesis Beyond the Phase-Locked Loop: Xiu/Nanometer Frequency Synthesis , 2012 .

[17]  Dinesh Bhatia,et al.  Network interface for NoC based architectures , 2007 .

[18]  Chun-Ming Hsu,et al.  Techniques for high-performance digital frequency synthesis and phase control , 2008 .

[19]  Ann Gordon-Ross,et al.  A Gigahertz Digital CMOS Divide-by-N Frequency Divider Based on a State Look-Ahead Structure , 2011, Circuits Syst. Signal Process..

[20]  Daniel J. Rogers.  Broadband Quantum Cryptography , 2010, Broadband Quantum Cryptography.

[21]  Jos L. Ayala.  Communication Architectures for Systems-on-Chip , 2011 .

[22]  Shahriar Mirabbasi,et al.  System-on-Chip: Reuse and Integration , 2006, Proceedings of the IEEE.