Model-based Design of Efficient LDPC Decoder Architectures

LDPC codes are finding increasing use in digital communication. The fast-paced evolution of new communication standards and ad-hoc applications requires rapid design iteration. Hand-coded RTL architectures generally provides high performance levels but slower the path to IP creation. In this paper we present a hardware LDPC decoder architecture generated with Vivado HLS from a generic SystemC behavioral model. We evaluate the performance of our approach and assess efficiency versus competing approaches. Throughput speedups between 1.1× and 16.7× are shown with an area improvements of 1.6× to 23.8×. A single LDPC decoder reaches up to 150 Mbps on a Xilinx Virtex-7 device for ten layered decoding iterations.

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