Controlling processor instruction execution using retired instruction counter

A system (10) and method 120 are disclosed for controlling processor instruction execution. A method for controlling a total number of instructions executed by a processor includes instructing the processor to execute instructions iteratively via multiple iterations 138, 140, 142, 144 until a predetermined time period has elapsed. A number of instructions executed in each iteration is less than a number of instructions executed in a prior iteration of the iterations, e.g. a geometric progression may be followed where the number of instructions executed in each iteration is roughly half that of the previous iteration. The total number of instructions executed during the predetermined time period is then determined, e.g. by reading or accessing a retired instruction counter (RIC). Other embodiments relate to synchronizing multiple processors (16,18, 20) at synchronization signals 124, 126, 130. A processor may send an indication and synchronize retired instruction counts (RICs) between replicated processors after each iteration is complete. Another embodiment relates to controlling a time period during which instructions are executed by instructing the processor to execute a first number of instructions via plural iterations, wherein a time period of each iteration is less than that of a prior iteration.