Law of large numbers system design

To date we have relied on the "Law of Large Numbers" below the device level to guarantee deterministic device behavior (e.g. dopant ratios, transition timing, electron state storage). However, at the nanoscale, we hope to build devices with small numbers of atoms or molecules (e.g. wires which are 3-10 atoms wide, diodes built from 1-10 molecules), and we hope to store state with small numbers of electrons (e.g. 10's). If we are to build devices at these scales, we will no longer be able to rely on the "Law of Large Numbers" below the device level. We must, instead, employ the "Law of Large Numbers" above the device level in order to obtain predictable behavior from atomic-scale phenomena which are statistical in nature. At the same time, the "Law of Large Numbers" can also help us by providing statistical differentiation at scales smaller than those we can pattern directly or economically using lithography. In this chapter, we examine various applications of the "Law of Large Numbers" above the device level to build reliable and controllable systems from nanoscale devices and processes that only have statistically predictable behavior.

[1]  Brent Keeth,et al.  DRAM Circuit Design: A Tutorial , 2000 .

[2]  J. F. Stoddart,et al.  A [2]Catenane-Based Solid State Electronically Reconfigurable Switch , 2000 .

[3]  Charles M. Lieber,et al.  Directed assembly of one-dimensional nanostructures into functional networks. , 2001, Science.

[4]  Ronald L. Rivest,et al.  Introduction to Algorithms , 1990 .

[5]  F. I. Osman Error-correction technique for random-access memories , 1982 .

[6]  Lars Samuelson,et al.  One-dimensional steeplechase for electrons realized , 2002 .

[7]  J. B. Angell,et al.  Redundancy for LSI Yield Enhancement , 1967 .

[8]  Alvin W. Drake,et al.  Fundamentals of Applied Probability Theory , 1967 .

[9]  Richard W. Hamming,et al.  Error detecting and error correcting codes , 1950 .

[10]  C. E. SHANNON,et al.  A mathematical theory of communication , 1948, MOCO.

[11]  Chin-Long Wey,et al.  On the design of a redundant programmable logic array (RPLA) , 1987 .

[12]  Jean-Claude Geffroy,et al.  Error Detecting and Correcting Codes , 2002 .

[13]  Christopher L. Brown,et al.  Introduction of [2]Catenanes into Langmuir Films and Langmuir-Blodgett Multilayers. A Possible Strategy for Molecular Information Storage Materials , 2000 .

[14]  John E. Savage,et al.  Decoding of stochastically assembled nanoarrays , 2004, IEEE Computer Society Annual Symposium on VLSI.

[15]  André DeHon,et al.  Stochastic assembly of sublithographic nanoscale interfaces , 2003 .

[16]  Edward J. McCluskey,et al.  Finite state machine synthesis with concurrent error detection , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[17]  Charles M. Lieber,et al.  Growth of nanowire superlattice structures for nanoscale photonics and electronics , 2002, Nature.

[18]  André DeHon,et al.  Array-based architecture for FET-based, nanoscale electronics , 2003 .

[19]  N. Melosh,et al.  Ultrahigh-Density Nanowire Lattices and Circuits , 2003, Science.

[20]  S. Trimberger,et al.  A reprogrammable gate array and applications , 1993 .

[21]  Edward J. McCluskey,et al.  Concurrent Error Detection and Testing for Large PLA's , 1982 .

[22]  Peidong Yang,et al.  Block-by-Block Growth of Single-Crystalline Si/SiGe Superlattice Nanowires , 2002 .

[23]  J. F. Stoddart,et al.  Nanoscale molecular-switch crossbar circuits , 2003 .

[24]  Lloyd R. Harriott,et al.  Limits of lithography , 2001, Proc. IEEE.

[25]  Nur A. Touba,et al.  Logic synthesis of multilevel circuits with concurrent error detection , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[26]  F. G. Maunsell A Problem in Cartophily , 1938 .

[27]  N. Macrae John Von Neumann , 1992 .

[28]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[29]  Michael J. Wilson,et al.  Nanowire-based sublithographic programmable logic arrays , 2004, FPGA '04.

[30]  S. E. Schuster Multiple word/bit line redundancy for semiconductor memories , 1978 .

[31]  Charles M. Lieber,et al.  Carbon nanotube-based nonvolatile random access memory for molecular computing , 2000, Science.

[32]  Stoddart,et al.  Electronically configurable molecular-based logic gates , 1999, Science.

[33]  Robert S. Swarz,et al.  Reliable Computer Systems: Design and Evaluation , 1992 .

[34]  Dongmok Whang,et al.  Large-scale hierarchical organization of nanowire arrays for integrated nanosystems , 2003 .

[35]  Erik H. Anderson,et al.  Nanoscale molecular-switch devices fabricated by imprint lithography , 2003 .

[36]  Dongmok Whang,et al.  Nanolithography Using Hierarchically Assembled Nanowire Masks , 2003 .