A 1-Kbit EEPROM in SIMOX technology for high-temperature applications up to 250/spl deg/C

A 1-Kbit high-temperature EEPROM memory module has been developed in a 1.6-/spl mu/m thin-film SIMOX technology. The memory array is based on single-poly EEPROM cells, which are erased and programmed by Fowler-Nordheim tunneling. Operation at elevated temperatures is achieved by a special array design, suitable for elimination of cell-disturb problems caused by temperature-induced leakage currents of the select transistors. High-voltage switching is done without PMOS transistors in order to avoid leakage currents due to the backgate effect. The memory module is designed for 5-V only operation and offers an access time of 260 ns at an operating temperature of 250/spl deg/C. At 250/spl deg/C, data retention of 3000 h and an endurance of 10000 erase/program cycles has been achieved. The area of the 1-Kbit memory module is 0.89/spl times/2.71 mm/sup 2/.

[1]  J.R. Yeargain,et al.  An 80 ns 32K EEPROM using the FETMOS cell , 1982, IEEE Journal of Solid-State Circuits.

[2]  G. Burbach,et al.  A single-poly EEPROM cell in SIMOX technology for high-temperature applications up to 250/spl deg/C , 1997, IEEE Electron Device Letters.

[3]  D. Flandre,et al.  High-temperature analog instrumentation system in thin-film fully-depleted SOI CMOS technology , 1998, 1998 Fourth International High Temperature Electronics Conference. HITEC (Cat. No.98EX145).

[4]  P.I. Suciu,et al.  A temperature- and process-tolerant 64K EEPROM , 1985, IEEE Journal of Solid-State Circuits.

[5]  G. Yaron,et al.  A 16K E/SUP 2/PROM employing new array architecture and designed-in reliability features , 1982, IEEE Journal of Solid-State Circuits.

[6]  H. Katto,et al.  Hi-MNOS II technology for a 64-kbit byte-erasable 5-V-only EEPROM , 1985, IEEE Transactions on Electron Devices.

[7]  Tetsuya Iizuka,et al.  An experimental 5-V-only 256-kbit CMOS EEPROM with a high-performance single-polysilicon cell , 1986 .

[8]  A. Renninger,et al.  A 5V-only 16K EEPROM utilizing oxynitride dielectrics and EPROM redundancy , 1982, 1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[9]  Sorin Cristoloveanu,et al.  Detailed analysis of edge effects in SIMOX-MOS transistors , 1992 .

[10]  Adam S. Sikora,et al.  Design automation of digital circuits for partially depleted SOI-technology , 1996, 1996 IEEE International SOI Conference Proceedings.

[11]  J. Colinge Silicon-on-Insulator Technology: Materials to VLSI , 1991 .

[12]  J. Colinge Silicon-on-Insulator Technology , 1991 .

[13]  B. W. Ohme,et al.  Control circuit design for high temperature linear regulators , 1998, 1998 Fourth International High Temperature Electronics Conference. HITEC (Cat. No.98EX145).

[14]  Silicon-on-insulator: CMOS devices and processes for high temperature applications , 1997 .

[15]  J. F. Dickson,et al.  On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique , 1976 .