A to-Bit 100MSPS 0.35 !lm Si CMOS Pipeline ADC
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Ning Ning | Lin Tang | Qi Yu | Xiang-zhan Wang | Hong-Bin Li | Mo-hua Yang
[1] P. Hurst,et al. A digital background calibration technique for time-interleaved analog-to-digital converters , 1998, IEEE J. Solid State Circuits.
[2] Myung-Jun Choe,et al. An 8 b 100 MSample/s CMOS pipelined folding ADC , 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).