Validation signature testing: A methodology for post-silicon validation of analog/mixed-signal circuits

Due to the use of scaled technologies, high levels of integration and high speeds of today's mixed-signal SoCs, the problem of validating correct operation of the SoC under electrical bugs and that of debugging yield loss due to unmodeled multi-dimensional variability effects is extremely challenging. Precise simulation of all electrical aspects of the design including the interfaces between digital and analog circuitry, coupling across power and ground planes, crosstalk, etc., across all process corners is very hard to achieve in a practical sense. The problem is expected to get worse as analog/mixed-signal/RF devices scale beyond the 45nm node and are more tightly integrated with digital systems than at present. In this context, a post-silicon validation methodology for analog/mixed-signal/RF SoCs is proposed that relies on the use of special stimulus designed to expose differences between observed DUT behavior and its predictive model. The corresponding error signature is then used to identify the likely “type” of electrical bug and its location in the design using nonlinear optimization algorithms. Results of trial experiments on RF devices are presented.

[1]  Kwang-Ting Cheng,et al.  An analysis of ATPG and SAT algorithms for formal verification , 2001, Sixth IEEE International High-Level Design Validation and Test Workshop.

[2]  Subhasish Mitra,et al.  IFRA: Instruction Footprint Recording and Analysis for post-silicon bug localization in processors , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[3]  Kenneth S. Kundert,et al.  Design of mixed-signal systems-on-a-chip , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Martin Freibothe,et al.  Formal Verification of the Quasi-Static Behavior of Mixed-Signal Circuits by Property Checking , 2006, Electron. Notes Theor. Comput. Sci..

[5]  Daniel G. Saab,et al.  Formal verification using bounded model checking: SAT versus sequential ATPG engines , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

[6]  Chris J. Myers,et al.  The Case for Analog Circuit Verification , 2006, Electron. Notes Theor. Comput. Sci..

[7]  David Lin,et al.  QED: Quick Error Detection tests for effective post-silicon validation , 2010, 2010 IEEE International Test Conference.

[8]  Abhijit Chatterjee,et al.  Optimized Multitone Test Stimulus Driven Diagnosis of RF Transceivers Using Model Parameter Estimation , 2011, 2011 24th Internatioal Conference on VLSI Design.

[9]  Kenneth S. Kundert,et al.  Verification of Complex Analog and RF IC Designs , 2007, Proceedings of the IEEE.

[10]  Jeongjin Roh,et al.  Verification of Delta-Sigma converters using adaptive regression modeling , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[11]  Bing J. Sheu,et al.  Nanometer mixed-signal system-on-a-chip design , 2002 .

[12]  Jacob A. Abraham,et al.  Verification of transient response of linear analog circuits , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[13]  Y.C. Pan,et al.  Mixed signal validation of the Intel/spl reg/ Pentium/spl reg/ 4 microprocessor power-up sequence , 2003, Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710).

[14]  Ernst Christen,et al.  Vhdl-ams---a hardware description language for analog and mixed-signal applications , 1999 .

[15]  Abhijit Chatterjee,et al.  Concurrent Device/Specification Cause–Effect Monitoring for Yield Diagnosis Using Alternate Diagnostic Signatures , 2012, IEEE Design & Test of Computers.

[16]  Masahiro Fujita,et al.  Model Checking Based on Sequential ATPG , 1999, CAV.

[17]  Gordon W. Roberts,et al.  Top-down analog design methodology using Matlab and Simulink , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[18]  K. Muhammad,et al.  Verification of RF SoCs: RF, analog, baseband and software , 2006, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006.

[19]  D. G. Saab,et al.  Verifying Properties Using Sequential ATPG , 2002 .

[20]  Nathaniel J. August.  A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel's Test Chips , 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).