ASIC Design of High-Speed Low-Power HDLC Controller

Combined with the engineering requirement, a high-speed low-power ASIC design of HDLC controllerbased on RS-485 bus is given in this paper.On principle of Top-Down design, this ASIC design usesmulti-techniques to reduce its die area and dynamic power,and overcomes some problems appeared frequently inapplication systems of the RS-485 circuits formed by the Standard Interface Chips. This design also improves thesystem reliability and reduces the system area.