Nanometer-Scale III-V MOSFETs

After 50 years of Moore's Law, Si CMOS, the mainstream logic technology, is on a course of diminishing returns. The use of new semiconductor channel materials with improved transport properties over Si offer the potential for device scaling to nanometer dimensions and continued progress. Among new channel materials, III-V compound semiconductors are particularly promising. InGaAs is currently the most attractive candidate for future III-V based n-type MOSFETs while InGaSb is of great interest for p-channel MOSFETs. At the point of most likely deployment, devices based on these semiconductors will have a highly three-dimensional architecture. This paper reviews recent progress toward the development of nanoscale III-V MOSFETs based on InGaAs and InGaSb with emphasis on scalable technologies and device architectures and relevant physics. Progress in recent times has been brisk but much work remains to be done before III-V CMOS can become a reality.

[1]  M. J. W. Rodwell,et al.  Record Ion (0.50 mA/µm at VDD = 0.5 V and Ioff = 100 nA/µm) 25 nm-gate-length ZrO2/InAs/InAlAs MOSFETs , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[2]  J. B. Boos,et al.  Hole mobility enhancement in In0.41Ga0.59Sb quantum-well field-effect transistors , 2011 .

[3]  D. Antoniadis,et al.  Off-State Leakage Induced by Band-to-Band Tunneling and Floating-Body Bipolar Effect in InGaAs Quantum-Well MOSFETs , 2014, IEEE Electron Device Letters.

[4]  M. Takenaka,et al.  Impact of interfacial InAs layers on Al2O3/GaSb metal-oxide-semiconductor interface properties , 2015 .

[5]  D. Antoniadis,et al.  InGaAs Quantum-Well MOSFET Arrays for Nanometer-Scale Ohmic Contact Characterization , 2016, IEEE Transactions on Electron Devices.

[6]  M. A. Pourghaderi,et al.  The influence of post-etch InGaAs fin profile on electrical performance , 2013 .

[7]  G. Dewey,et al.  High-performance 40nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (VCC=0.5V) logic applications , 2008, 2008 IEEE International Electron Devices Meeting.

[8]  Erik Lind,et al.  Extrinsic and Intrinsic Performance of Vertical InAs Nanowire MOSFETs on Si Substrates , 2013, IEEE Transactions on Electron Devices.

[9]  P. Ye,et al.  GaSb Inversion-Mode PMOSFETs With Atomic-Layer-Deposited Al 2 O 3 as Gate Dielectric , 2011 .

[10]  Mitsuru Takenaka,et al.  Self-Aligned Metal Source/Drain InxGa1-xAs n-Metal?Oxide?Semiconductor Field-Effect Transistors Using Ni?InGaAs Alloy , 2011 .

[11]  B. Duriez,et al.  InAs N-MOSFETs with record performance of Ion = 600 μA/μm at Ioff = 100 nA/μm (Vd = 0.5 V) , 2013, 2013 IEEE International Electron Devices Meeting.

[12]  Mark Y. Liu,et al.  A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size , 2014, 2014 IEEE International Electron Devices Meeting.

[13]  D. A. Antoniadis,et al.  Sub-30 nm InAs Quantum-Well MOSFETs with self-aligned metal contacts and Sub-1 nm EOT HfO2 insulator , 2012, 2012 International Electron Devices Meeting.

[15]  Dimitri A. Antoniadis,et al.  Novel intrinsic and extrinsic engineering for high-performance high-density self-aligned InGaAs MOSFETs: Precise channel thickness control and sub-40-nm metal contacts , 2014, 2014 IEEE International Electron Devices Meeting.

[16]  I. Lindau,et al.  Unified defect model and beyond , 1980 .

[17]  Suzanne E. Mohney,et al.  Factors controlling the resistance of Ohmic contacts to n-InGaAs , 2012 .

[18]  M. Rodwell,et al.  Highly Scalable Raised Source/Drain InAs Quantum Well MOSFETs Exhibiting $I_{{\scriptstyle {\rm ON}}}=482~\mu{\rm A}/\mu{\rm m}$ at $I_{{\scriptstyle {\rm OFF}}}=100~{\rm nA}/\mu{\rm m}$ and $V_{\rm DD}=0.5~{\rm V}$ , 2014, IEEE Electron Device Letters.

[19]  G. Dewey,et al.  Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/gate-to-source separation , 2011, 2011 International Electron Devices Meeting.

[20]  D-H Kim,et al.  InGaAs MOSFETs for CMOS: Recent advances in process technology , 2013, 2013 IEEE International Electron Devices Meeting.

[21]  Xiao Gong,et al.  In0.7Ga0.3As Channel n-MOSFET with Self-Aligned Ni–InGaAs Source and Drain , 2011 .

[22]  Dimitri A. Antoniadis,et al.  Record Maximum Transconductance of 3.45 mS/ $\mu \text{m}$ for III-V FETs , 2016, IEEE Electron Device Letters.

[23]  E. Lind,et al.  High transconductance self-aligned gate-last surface channel In0.53Ga0.47As MOSFET , 2011, 2011 International Electron Devices Meeting.

[24]  Quantum-size effects in sub 10-nm fin width InGaAs FinFETs , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[25]  D. Antoniadis,et al.  Impact of Intrinsic Channel Scaling on InGaAs Quantum-Well MOSFETs , 2015, IEEE Transactions on Electron Devices.

[26]  J. D. del Alamo.  Nanometre-scale electronics with III-V compound semiconductors. , 2011, Nature.

[27]  InGaAs Double-gate fin-sidewall MOSFET , 2014, 72nd Device Research Conference.

[28]  Susanne Stemmer,et al.  Comparison of methods to quantify interface trap densities at dielectric/III-V semiconductor interfaces , 2010 .

[29]  P. Ye,et al.  GaSb Inversion-Mode PMOSFETs With Atomic-Layer-Deposited $\hbox{Al}_{2}\hbox{O}_{3}$ as Gate Dielectric , 2011, IEEE Electron Device Letters.

[30]  K. H. Chen,et al.  Passivation of GaSb using molecular beam epitaxy Y2O3 to achieve low interfacial trap density and high-performance self-aligned inversion-channel p-metal-oxide-semiconductor field-effect-transistors , 2014 .

[31]  Peide D. Ye,et al.  Fundamentals of III-V Semiconductor MOSFETs , 2010 .

[32]  A. Alian,et al.  A Combined Interface and Border Trap Model for High-Mobility Substrate Metal–Oxide–Semiconductor Devices Applied to $\hbox{In}_{0.53} \hbox{Ga}_{0.47}\hbox{As}$ and InP Capacitors , 2011, IEEE Transactions on Electron Devices.

[33]  Erik Lind,et al.  Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[34]  Lars-Erik Wernersson,et al.  III–V compound semiconductor transistors—from planar to nanowire structures , 2014 .

[35]  T. Fukui,et al.  A III–V nanowire channel on silicon for high-performance vertical transistors , 2012, Nature.

[36]  S. Datta,et al.  Indium arsenide (InAs) single and dual quantum-well heterostructure FinFETs , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[37]  C. Merckling,et al.  An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[38]  J. D. del Alamo,et al.  Vertical nanowire InGaAs MOSFETs fabricated by a top-down approach , 2013, 2013 IEEE International Electron Devices Meeting.

[39]  Peide D. Ye,et al.  GaAs metal–oxide–semiconductor field-effect transistor with nanometer-thin dielectric grown by atomic layer deposition , 2003 .

[40]  P. D. Kirsch,et al.  Sub-100 nm InGaAs quantum-well (QW) tri-gate MOSFETs with Al2O3/HfO2 (EOT < 1 nm) for low-power logic applications , 2013, 2013 IEEE International Electron Devices Meeting.

[41]  S. Jang,et al.  Low interface trap density Al2O3/In0.53Ga0.47As MOS capacitor fabricated on MOCVD-grown InGaAs epitaxial layer on Si substrate , 2014 .

[42]  Mario G. Ancona,et al.  High mobility p-channel HFETs using strained Sb-based materials , 2007 .

[43]  J. Plummer,et al.  Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's , 1997, IEEE Electron Device Letters.

[44]  A Test Structure to Characterize Nano-Scale Ohmic Contacts in III-V MOSFETs , 2014, IEEE Electron Device Letters.

[45]  J. B. Boos,et al.  Device quality Sb-based compound semiconductor surface: A comparative study of chemical cleaning , 2011 .

[46]  K. Saraswat,et al.  Optimization of the Al 2 O 3 / GaSb Interface and a High-Mobility GaSb pMOSFET , 2011 .

[47]  Xin Zhao,et al.  Nanometer-Scale Vertical-Sidewall Reactive Ion Etching of InGaAs for 3-D III-V MOSFETs , 2014, IEEE Electron Device Letters.

[48]  Effects of ozone post deposition treatment on interfacial and electrical characteristics of atomic-layer-deposited Al2O3 and HfO2 films on GaSb substrates , 2013, 1310.6457.

[49]  Luping Shi,et al.  III–V Multiple-Gate Field-Effect Transistors With High-Mobility $\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ Channel and Epi-Controlled Retrograde-Doped Fin , 2011, IEEE Electron Device Letters.

[50]  P. Ye,et al.  Capacitance-voltage studies on enhancement-mode InGaAs metal-oxide-semiconductor field-effect transistor using atomic-layer-deposited Al2O3 gate dielectric , 2006 .

[51]  A. Lochtefeld,et al.  (Invited) Aspect Ratio Trapping: A Unique Technology for Integrating Ge and III-Vs with Silicon CMOS , 2010 .

[52]  High-performance CMOS-compatible self-aligned In0.53Ga0.47As MOSFETs with GMSAT over 2200 µS/µm at VDD = 0.5 V , 2014, 2014 IEEE International Electron Devices Meeting.

[53]  Nanoscale Mo Ohmic Contacts to III–V Fins , 2015, IEEE Electron Device Letters.

[54]  D. Antoniadis,et al.  Physics and Mitigation of Excess OFF-State Current in InGaAs Quantum-Well MOSFETs , 2015, IEEE Transactions on Electron Devices.

[55]  Mark J. W. Rodwell,et al.  Lower limits to metal-semiconductor contact resistance: Theoretical models and experimental data , 2013 .

[56]  Diederik Verkest,et al.  Vertical GAAFETs for the Ultimate CMOS Scaling , 2015, IEEE Transactions on Electron Devices.

[57]  J. B. Boos,et al.  Development of high-k dielectric for antimonides and a sub 350°C III–V pMOSFET outperforming Germanium , 2010, 2010 International Electron Devices Meeting.

[58]  del Alamo,et al.  The High-Electron Mobility Transistor at 30: Impressive Accomplishments and Exciting Prospects , 2011 .

[59]  Xin Zhao,et al.  High aspect ratio InGaAs FinFETs with sub-20 nm fin width , 2016, 2016 IEEE Symposium on VLSI Technology.

[60]  S. Datta,et al.  Impact of Transistor Architecture (Bulk Planar, Trigate on Bulk, Ultrathin-Body Planar SOI) and Material (Silicon or III–V Semiconductor) on Variation for Logic and SRAM Applications , 2013, IEEE Transactions on Electron Devices.

[61]  G. Curello,et al.  A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications , 2012, 2012 International Electron Devices Meeting.

[62]  K. Lau,et al.  30-nm Inverted $\hbox{In}_{0.53}\hbox{Ga}_{0.47} \hbox{As}$ MOSHEMTs on Si Substrate Grown by MOCVD With Regrown Source/Drain , 2012, IEEE Electron Device Letters.

[63]  J. B. Boos,et al.  Optimization of the $\hbox{Al}_{2}\hbox{O}_{3}/ \hbox{GaSb}$ Interface and a High-Mobility GaSb pMOSFET , 2011, IEEE Transactions on Electron Devices.

[64]  J. B. Boos,et al.  Ultralow Resistance Ohmic Contacts for p-Channel InGaSb Field-Effect Transistors , 2015, IEEE Electron Device Letters.

[65]  D. Antoniadis,et al.  A Novel Digital Etch Technique for Deeply Scaled III-V MOSFETs , 2014, IEEE Electron Device Letters.

[66]  A. Vais,et al.  Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[67]  Luping Shi,et al.  III-V Multiple-Gate Field-Effect Transistors With High-Mobility In 0.7 Ga 0.3 As Channel and Epi-Controlled Retrograde-Doped Fin , 2011 .

[68]  Xiuling Li,et al.  III–V Nanowire Transistors for Low-Power Logic Applications: A Review and Outlook , 2016, IEEE Transactions on Electron Devices.

[69]  Y. Yeo,et al.  InAs FinFETs With $\textrm {H}_{\mathrm {fin}}=20$ nm Fabricated Using a Top–Down Etch Process , 2016, IEEE Electron Device Letters.

[70]  P. D. Ye,et al.  First experimental demonstration of gate-all-around III–V MOSFETs by top-down approach , 2011, 2011 International Electron Devices Meeting.

[71]  J. B. Boos,et al.  Mobility enhancement in strained p-InGaSb quantum wells , 2007 .

[72]  Jean-Pierre Colinge,et al.  Device design guidelines for nano-scale MuGFETs , 2007 .

[73]  S. Takagi,et al.  High hole mobility front-gate InAs/InGaSb-OI single structure CMOS on Si , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[74]  C. Hsieh,et al.  An Ultralow-Resistance Ultrashallow Metallic Source/Drain Contact Scheme for III–V NMOS , 2012, IEEE Electron Device Letters.

[75]  P. Wambacq,et al.  Vertical device architecture for 5nm and beyond: Device & circuit implications , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[76]  J. D. del Alamo,et al.  An InGaSb p-channel FinFET , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[77]  Daehyun Kim,et al.  60 nm self-aligned-gate InGaAs HEMTs with record high-frequency characteristics , 2010, 2010 International Electron Devices Meeting.