A unified framework for race analysis of asynchronous networks

A unified framework is developed for the study of asynchronous circuits of both gate and MOS type. A basic network model consisting of a directed graph and a set of vertex excitation functions is introduced. A race analysis model, using three values (0, 1, and x), is developed for studying state transitions in the network. It is shown that the results obtained using this model are equivalent to those using ternary simulation. It is also proved that the set of state variables can be reduced to a minimum size set of feedback variables, and the analysis still yields both the correct state transitions and output hazard information. Finally, it is shown how the general results above are applicable to both gate and MOS circuits.

[1]  David S. Johnson,et al.  Computers and In stractability: A Guide to the Theory of NP-Completeness. W. H Freeman, San Fran , 1979 .

[2]  Theodore M. Booth.  Demonstrating hazards in sequential relay circuits , 1963, SWCT.

[3]  Stephen H. Unger,et al.  Asynchronous sequential switching circuits , 1969 .

[4]  Edward B. Eichelberger,et al.  Hazard Detection in Combinational and Sequential Switching Circuits , 1964, IBM J. Res. Dev..

[5]  Randal E. Bryant,et al.  Algorithmic Aspects of Symbolic Switch Network Analysis , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[7]  Raymond E Miller.  Switching theory , 1979 .

[8]  Edward J. McCluskey,et al.  Signal Flow Graph Techniques for Sequential Circuit State Diagrams , 1963, IEEE Trans. Electron. Comput..

[9]  R.W. Hyndman,et al.  Digital networks , 1977, Proceedings of the IEEE.

[10]  Randall E. Bryant.  Race Detection in MOS Circuits By Ternary Simulation , 1983 .

[11]  Michael Yoeli,et al.  Application of Ternary Algebra to the Study of Static Hazards , 1964, JACM.

[12]  Carl-Johan H. Seger,et al.  A Characterization of Ternary Simulation of Gate Networks , 1987, IEEE Transactions on Computers.

[13]  David A. Huffman,et al.  The synthesis of sequential switching circuits , 1954 .

[14]  Glen G. Langdon.  Analysis of Asynchronous Circuits Under Different Delay Assumptions , 1968, IEEE Transactions on Computers.

[15]  Michael Yoeli,et al.  On a Ternary Model of Gate Networks , 1979, IEEE Transactions on Computers.

[16]  Thomas Lengauer,et al.  An analysis of ternary simulation as a tool for race detection in digital MOS circuits , 1986, Integr..

[17]  Michael Yoeli,et al.  Combinational static CMOS networks , 1987, Integr..

[18]  Edward J. McCluskey,et al.  Transients in combinational logic circuits , 1962 .

[19]  Randal E. Bryant,et al.  Boolean Analysis of MOS Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Melvin A. Breuer.  A Note on Three-Valued Logic Simulation , 1972, IEEE Transactions on Computers.

[21]  Randal E. Bryant,et al.  A Switch-Level Model and Simulator for MOS Digital Systems , 1984, IEEE Transactions on Computers.

[22]  Carl-Johan H. Seger,et al.  An Optimistic Ternary Simulation of Gate Races , 1988, Theor. Comput. Sci..