Non-buried layer double deep N well high-voltage isolation N-type LDMOS and method for manufacturing N-type LDMOS devices

The present invention discloses a double non-buried layer deep N-well isolation N-type the LDMOS high voltage, having a first deep N-well on a P-type silicon substrate, having a first deep N-well P-well and a plurality of isolation structures; of a deep N-well as the gate electrode, a gate on one end of the P-well, the other end of the isolation structure; the first deep N well having a heavily doped N-type region, N + drain region of the LDMOS device , P well having a heavily doped N-type region, an N-type heavily doped region is a source of the LDMOS device; below the second P well having a deep N-well below the heavily doped N-type region having a third deep N type well, a second, a third depth and the deep N-implant concentration greater than the depth of the first well and the deep N-well implant concentration. The present invention also discloses a method for producing N-type LDMOS device. The present invention allows the PNP in the vertical and horizontal directions through the drain-side extension region breakdown voltage and specific on-resistance optimization are controlled, the process is simple and flexible, easy to implement, a substantial decline compared to + buried layer epitaxy method cost of the process.