Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology

In this paper, a novel low-power and highly reliable radiation hardened memory cell (RHM-12T) using 12 transistors is proposed to provide enough immunity against single event upset in TSMC 65 nm CMOS technology. The obtained results show that the proposed cell can not only tolerate upset at its any sensitive node regardless of upset polarity and strength, but also recover from multiple-node upset induced by charge sharing on the fixed nodes independent of the stored value. Moreover, the proposed cell has comparable or lower overheads in terms of static power, area and access time compared with previous radiation hardened memory cells.

[1]  Salvatore Pontarelli,et al.  Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Michael Nicolaidis,et al.  SEU-tolerant SRAM design based on current monitoring , 1994, Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing.

[3]  B. Arun Kumar,et al.  Efficient Majority Logic Fault Detection with Difference-Set Codes for Memory Applications , 2013 .

[4]  Yong-Bin Kim,et al.  A novel sort error hardened 10T SRAM cells for low voltage operation , 2012, 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS).

[5]  E. Ibe,et al.  Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule , 2010, IEEE Transactions on Electron Devices.

[6]  T. Calin,et al.  Upset hardened memory design for submicron CMOS technology , 1996 .

[7]  M. Tech ERROR DETECTION IN MAJORITY LOGIC DECODING OF EUCLIDEAN GEOMETRY LOW DENSITY PARITY CHECK (EG-LDPC) CODES , 2014 .

[8]  Chia-Hsiung Kao,et al.  Single-ended SRAM with high test coverage and short test time , 2000, IEEE Journal of Solid-State Circuits.

[9]  M. Alderighi,et al.  Comparison of the Susceptibility to Soft Errors of SRAM-Based FPGA Error Correction Codes Implementations , 2012, IEEE Transactions on Nuclear Science.

[10]  Qiang Zhao,et al.  Novel Mixed Codes for Multiple-Cell Upsets Mitigation in Static RAMs , 2013, IEEE Micro.

[11]  Chaitali Chakrabarti,et al.  Product Code Schemes for Error Correction in MLC NAND Flash Memories , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  P. Roche,et al.  Underground Experiment and Modeling of Alpha Emitters Induced Soft-Error Rate in CMOS 65 nm SRAM , 2012, IEEE Transactions on Nuclear Science.

[13]  Ching-Te Chuang,et al.  Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  Ivan R. Linscott,et al.  LEAP: Layout Design through Error-Aware Transistor Positioning for soft-error resilient sequential cell design , 2010, 2010 IEEE International Reliability Physics Symposium.

[15]  R. Baumann Soft errors in advanced semiconductor devices-part I: the three radiation sources , 2001 .

[16]  B.L. Bhuva,et al.  Charge Collection and Charge Sharing in a 130 nm CMOS Technology , 2006, IEEE Transactions on Nuclear Science.

[17]  S. Jahinuzzaman,et al.  A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability , 2009, IEEE Transactions on Nuclear Science.

[18]  Yong-Bin Kim,et al.  Analysis and Design of Nanoscale CMOS Storage Elements for Single-Event Hardening With Multiple-Node Upset , 2012, IEEE Transactions on Device and Materials Reliability.

[19]  Cecilia Metra,et al.  High-Performance Robust Latches , 2010, IEEE Transactions on Computers.

[20]  Mark F. Flanagan,et al.  Multiple Cell Upset Correction in Memories Using Difference Set Codes , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[21]  Lloyd W. Massengill,et al.  Basic mechanisms and modeling of single-event upset in digital microelectronics , 2003 .

[22]  H. Hughes,et al.  Radiation effects and hardening of MOS technology: devices and circuits , 2003 .

[23]  Peter Hazucha,et al.  Characterization of soft errors caused by single event upsets in CMOS processes , 2004, IEEE Transactions on Dependable and Secure Computing.

[24]  Dhiraj K. Pradhan,et al.  Matrix Codes for Reliable and Cost Efficient Memory Chips , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[25]  D. C. Bossen,et al.  Orthogonal latin square codes , 1970 .

[26]  Yong-Bin Kim,et al.  A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[27]  P. E. Dodd,et al.  Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction , 2013, IEEE Transactions on Nuclear Science.

[28]  José G. Delgado-Frias,et al.  Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[29]  Dan Alexandrescu,et al.  Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[30]  Ken Choi,et al.  High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.