Modulo 2n±1 Adder Design Using Select-Prefix Blocks

We present new design methods for modulo 2/sup n//spl plusmn/1 adders. We use the same select-prefix addition block for both modulo 2/sup n/-1 and diminished-one modulo 2/sup n/+1 adder design. VLSI implementations of the proposed adders in static CMOS show that they achieve an attractive combination of speed and area costs.

[1]  John J. Shedletsky.  Comment on the Sequential and Indeterminate Behavior of an End-Around-Carry Adder , 1977, IEEE Trans. Computers.

[2]  Fred Halsall,et al.  Data communications, computer networks and open systems (3. ed.) , 1995, Electronic-systems engineering series.

[3]  Wolfgang Fichtner,et al.  A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm , 1994 .

[4]  R. Ramaswami,et al.  Book Review: Design and Analysis of Fault-Tolerant Digital Systems , 1990 .

[5]  Yutai Ma.  A Slimplified Architecture for Modulo (2n + 1) Multiplication , 1998, IEEE Trans. Computers.

[6]  K. Tsukada,et al.  Data communications , 1981, IEEE Communications Magazine.

[7]  Mansoor-Uz-Zafar Dawood.  Error Control Coding with Investigation Modling and Designing of Self Checker Circuits for Computer Systems. , 2002 .

[8]  Simon Knowles,et al.  A family of adders , 1999, Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336).

[9]  Graham A. Jullien,et al.  A look-up table VLSI design methodology for RNS structures used in DSP applications , 1987 .

[10]  Reto Zimmermann,et al.  Efficient VLSI implementation of modulo (2/sup n//spl plusmn/1) addition and multiplication , 1999, Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336).

[11]  MaYutai.  A Simplified Architecture for Modulo (2n + 1) Multiplication , 1998 .

[12]  W K Jenkins.  Recent advances in residue number techniques for recursive digital filtering , 1979 .

[13]  Fred Halsall,et al.  Data communications, computer networks and open systems (3. ed.) , 1995, Electronic-systems engineering series.

[14]  Costas Efstathiou,et al.  Area-time efficient modulo 2/sup n/-1 adder design , 1994 .

[15]  Barry W. Johnson.  Design & analysis of fault tolerant digital systems , 1988 .

[16]  M. Etzel,et al.  The design of specialized residue classes for efficient recursive digital filter realization , 1982 .

[17]  Xuejia Lai,et al.  A Proposal for a New Block Encryption Standard , 1991, EUROCRYPT.

[18]  K. Elleithy,et al.  Fast and flexible architectures for RNS arithmetic decoding , 1992 .

[19]  L. Leibowitz.  A simplified binary arithmetic for the Fermat number transform , 1976 .

[20]  Andreas Curiger.  VLSI architectures for computations in finite rings and fields , 1993 .

[21]  Israel Koren.  Computer arithmetic algorithms , 1993 .

[22]  W. Kenneth Jenkins,et al.  The use of residue number systems in the design of finite impulse response digital filters , 1977 .

[23]  Thammavarapu R. N. Rao,et al.  Error coding for arithmetic processors , 1974 .

[24]  Haridimos T. Vergos,et al.  Diminished-One Modulo 2n+1 Adder Design , 2002, IEEE Trans. Computers.

[25]  C. Efstathiou,et al.  AREA-TIME EFFICIENT MODULO 2N-1 ADDER DESIGN , 1994 .

[26]  Haridimos T. Vergos,et al.  High-Speed Parallel-Prefix Modulo 2n-1 Adders , 2000, IEEE Trans. Computers.

[27]  Akhilesh Tyagi,et al.  A Reduced-Area Scheme for Carry-Select Adders , 1993, IEEE Trans. Computers.

[28]  Harold S. Stone,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.

[29]  Michael A. Soderstrand,et al.  Residue number system arithmetic: modern applications in digital signal processing , 1986 .