Finding Solutions to the Challenges in Package Interconnect Reliability

The microelectronic industry has continuously driven for greater integration of functionality and capability. This has led to some significant challenges for the industry. For example, to improve electrical performance, materials with low dielectric constants are being added to the silicon structures. These fragile materials in silicon interconnect layers present a significant challenge to the development of reliable package assembly processes. Similarly, the introduction of new features has led to the need for smaller, weaker interconnects between the package and the system board. Recently, these trends have been coupled with changes to the operating environment for electronic devices. With the growing trend toward mobile computing, the risk of interconnect damage from devices being dropped has grown. This is further complicated by the legal requirement to remove lead-containing materials from the package. This requirement affects the package interconnects by eliminating solder materials that have been traditionally used, whose behavior is well understood and quantified. The traditional approach to resolving such challenges involves finding solutions through large designed experiments to optimize the design, material, and process choices. These methods have met with difficulty due to the complexity and interdependency of the issues. In this paper we look at the application of new engineering mechanics tools and methods to better understand the fundamentals of package reliability. To determine the reliability, one must be able to assess both sides of the reliability equation: the stress imposed by the loading condition and the material strength. In general, if the strength of the interconnect exceeds the stress applied throughout the life of the package, then it will be reliable. While it is not always possible to accurately predict and quantify both sides, the techniques discussed can help engineers make better judgments and can provide direction to technology development. In this paper we describe three case studies using the approach described above. The first case study describes how bump pull/shear metrologies are used to understand the impact of various assembly and silicon fabrication processes on the silicon interconnect strength. The second case study provides a thorough analysis of second-level interconnect reliability (BGA) under shock loading conditions in laptops. The last case study shows how these measures can be used to enhance the material selection process in selecting a second-generation lead-free solder material. This approach has lead to the successful launch of lead-free package technologies with higher density interconnects.