VLSI Architectures For Image Filtering

This paper presents a study of problems encountered when implementing real time image filters. First, the complexity of the algorithms is studied, according to the peculiarities of applications. Then the problem of the system design and its organisation is presented and differents chip architectures are described for various tradeoffs between the architectural parameters. A new architecture used also for motion estimation is mentioned. In the last chapter the problems of the computation operator design is addressed, with elements on different choices for internal oganization of the computation, pipelining and computation format. This study is based on many applications for which VLSI architectures have already been designed and reported. For some of them chip are currently implemented in our laboratories. Linear filtering has been selected for illustration purpose, but this study is also concerned with many other problems of real time image processing, all exhibiting the common feature of a great importance in the architecture of the global managament of data communication and storage.

[1]  Peter Alexander Ruetz.  Architectures and design techniques for real-time image processing , 1990, Other Conferences.

[2]  Ting-Chung Chen,et al.  A 16X16 Discrete Cosine Transform Chip , 1987, Other Conferences.

[3]  Bede Liu,et al.  A new hardware realization of digital filters , 1974 .

[4]  H. Maitre,et al.  A single chip VLSI architecture for a real time stereo vision processor , 1988, ICASSP-88., International Conference on Acoustics, Speech, and Signal Processing.

[5]  F. Jutand,et al.  VLSI Architecture for a one chip video median filter , 1985, ICASSP '85. IEEE International Conference on Acoustics, Speech, and Signal Processing.

[6]  F. Jutand,et al.  A single chip video rate 16×16 discrete cosine transform , 1986, ICASSP '86. IEEE International Conference on Acoustics, Speech, and Signal Processing.

[7]  H. T. Kung.  Why systolic architectures? , 1982, Computer.

[8]  C. C. Stearns,et al.  A reconfigurable 64-tap transversal filter , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[9]  P. A. Ruetz,et al.  The architectures and design of a 20-MHz real-time DSP chip set , 1989 .