Hough transform algorithm for FPGA implementation

A novel algorithm for computing the Hough transform (HT) is introduced. The basic idea consists in using a combination of an incremental method with the usual HT expression to join circuit performance and accuracy requirements. The algorithm is primarily developed to fit field programmable gate arrays (FPGA) implementation that have become a competitive alternative for high performance digital signal processing applications. The induced architecture presents a high degree of regularity, making its VLSI implementation very straight forward. This implementation may be achieved by a generator program, assuring a shorter design cycle and a lower cost. For illustration, implementation results of an HT parameter extractor for 8-bit image pixels is given.

[1]  Josef Kittler,et al.  A survey of the hough transform , 1988, Comput. Vis. Graph. Image Process..

[2]  Mohammed Atiquzzaman.  Pipelined implementation of the multiresolution Hough transform in a pyramid multiprocessor , 1994, Pattern Recognit. Lett..

[3]  Hugo De Man,et al.  Deriving ASIC architectures for the Hough transform , 1990, Parallel Comput..

[4]  Alok N. Choudhary,et al.  Implementation and Evaluation of Hough Transform Algorithms on a Shared-Memory Multiprocessor , 1991, J. Parallel Distributed Comput..

[5]  Erik L. Dagless,et al.  Hough transform for transputer arrays , 1989 .

[6]  Hiroyasu Koshimizu,et al.  FIHT2 Algorithm: A Fast Incremental Hough Transform , 1990, MVA.

[7]  Mark Sandler,et al.  Analogue implementation of the Hough transform , 1991 .

[8]  D. Ben-Tzvi,et al.  Synchronous multiprocessor implementation of the Hough transform , 1990, Comput. Vis. Graph. Image Process..

[9]  Roger Woods,et al.  Implementation of the 2D DCT using a Xilinx XC6264 FPGA , 1997, 1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing.

[10]  Samir Tagzout,et al.  Compact parallel multipliers using the sign-generate method in FPGA , 1998 .