HSIS: A BDD-Based Environment for Formal Verification

Functional and timing verification are currently the bottlenecks in many design efforts. Simulation and emulation are extensively used for verification. Formal verification is now gaining acceptance in advanced design groups. This has been facilitated by the use of binary decision diagrams (BDDs). This paper describes the essential features of HSIS, a BDD-based environment for formal verification: 1. Open language design, made possible by using a compact and expressive intermediate format known as BLIF-MV. Currently, a synthesis subset of Verilog is supported. 2. Support for both model checking and language containment in a single unified environment, using expressivefairness constraints. 3. Efficient BDD-based algorithms. 4. Debugging environment for both language containment and model checking. 5. Automatic algorithms for the early quantification problem. 6. Support for state minimization using bisimulation and similar techniques. HSIS allows us to experiment with formal verification techniques on a variety of design problems. It also provides an environment for further research in formal verification.

[1]  Robin Milner,et al.  Communication and concurrency , 1989, PHI Series in computer science.

[2]  Felice Balarin,et al.  Verilog HDL Modeling Styles for Formal Verification , 1993, CHDL.

[3]  M. Gordon.  HOL: A Proof Generating System for Higher-Order Logic , 1988 .

[4]  Robert P. Kurshan,et al.  Software for analytical development of communications protocols , 1990, AT&T Technical Journal.

[5]  Edmund M. Clarke,et al.  Symbolic Model Checking: 10^20 States and Beyond , 1990, Inf. Comput..

[6]  Alan J. Hu,et al.  Protocol verification as a hardware design aid , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[7]  Robert K. Brayton,et al.  Efficient omega-Regular Language Containment , 1992, CAV.

[8]  R. P. Kurshan,et al.  Reducibility in analysis of coordination , 1988 .

[9]  Robert K. Brayton,et al.  Heuristic algorithms for early quantification and partial product minimization , 1993 .

[10]  Robert K. Brayton,et al.  Heuristic Algorithms for Early Quantification and Partial , 1994 .

[11]  R. Brayton,et al.  B L F-M V An Interchange Format for Design Verification and Synthesis , 1991 .

[12]  Robert K. Brayton,et al.  BDD-Based Debugging Of Design Using Language Containment and Fair CTL , 1993, CAV.

[13]  R. P. Kurshan,et al.  Automata-theoretic verification of coordinating processes , 1994 .

[14]  Robert S. Boyer,et al.  A computational logic handbook , 1979, Perspectives in computing.

[15]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[16]  Robert K. Brayton,et al.  BDD Variable Ordering for Interacting Finite State Machines , 1994, 31st Design Automation Conference.

[17]  Robert K. Brayton,et al.  A Unified Approach to Language Containment and Fair CTL Model Checking , 1993, 30th ACM/IEEE Design Automation Conference.

[18]  Olivier Coudert,et al.  A unified framework for the formal verification of sequential circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[19]  Sérgio Vale Aguiar Campos,et al.  Symbolic Model Checking , 1993, CAV.

[20]  Chin-Laung Lei,et al.  Modalities for model checking (extended abstract): branching time strikes back , 1985, POPL.

[21]  E. Emerson,et al.  Modalities for model checking (extended abstract): branching time strikes back , 1985, ACM-SIGACT Symposium on Principles of Programming Languages.

[22]  Vigyan Singhal,et al.  Edge-Streett/Edge-Rabin Automata Environment for Formal Verification Using Language Containment , 1994 .

[23]  Szu-Tsung Cheng,et al.  Compiling Verilog into Automata , 1994 .

[24]  Robert K. Brayton,et al.  Edge-Streett/ Edge-Rabin Automata Environment for , 1994 .