We present in this paper the design and the implementation of the optimized Canny-Deriche edge detector.
After a brief reminder of the filter's equations, we expose different techniques to speed up the sampling rate of the IIR filter . In
particular, to improve throughput rate of the IIR filter, we present a look-ahead with a decomposition technique . This method leads
us to design a first chip, which performs over 20 Mhz sampling rate with a silicon area of 60 mm2 . Using a local register retiming
method, we have designed a second circuit, which is able to process a pixel in 33 MHz with a silicon area of 30 mm 2 . These two
approaches are compared . This work leads us to an ASIC designed in a CMOS 1 p,m technology and succesfully tested .