Statistical data correction for unreliable memories

In this paper, we introduce a statistical data-correction framework that aims at improving the DSP system performance in presence of unreliable memories. The proposed signal processing framework implements best-effort error mitigation for signals that are corrupted by defects in unreliable storage arrays using a statistical correction function extracted from the signal statistics, a data-corruption model, and an application-specific cost function. An application example to communication systems demonstrates the efficacy of the proposed approach.

[1]  Christoph Roth,et al.  On the exploitation of the inherent error resilience of wireless systems under unreliable silicon , 2012, DAC Design Automation Conference 2012.

[2]  Kiarash Amiri,et al.  A combined channel and hardware noise resilient Viterbi decoder , 2010, 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers.

[3]  Gerald Matz,et al.  The effect of unreliable LLR storage on the performance of MIMO-BICM , 2010, 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers.

[4]  Vivek De,et al.  Design and reliability challenges in nanometer technologies , 2004, Proceedings. 41st Design Automation Conference, 2004..

[5]  Kaushik Roy,et al.  Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era , 2010, Proceedings of the IEEE.

[6]  Hubert Kaeslin.  Digital Integrated Circuit Design: Outlook , 2008 .

[7]  Christoph Roth,et al.  Data mapping for unreliable memories , 2012, 2012 50th Annual Allerton Conference on Communication, Control, and Computing (Allerton).

[8]  Lara Dolecek,et al.  Gallager B LDPC Decoder with Transient and permanent errors , 2013, 2013 IEEE International Symposium on Information Theory.

[9]  Helmut Bölcskei,et al.  Soft–Input Soft–Output Single Tree-Search Sphere Decoding , 2009, IEEE Transactions on Information Theory.

[10]  Swarup Bhunia,et al.  Low-Power Variation-Tolerant Design in Nanometer Silicon , 2011 .

[11]  A. Burg,et al.  A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS , 2010, 2010 IEEE Asian Solid-State Circuits Conference.

[12]  Norbert Wehn,et al.  A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder , 2008, 2008 Design, Automation and Test in Europe.

[13]  Marten van Dijk,et al.  Correcting systematic mismatches in computed log-likelihood ratios , 2003, Eur. Trans. Telecommun..

[14]  Jan M. Rabaey,et al.  Low Power Design Essentials , 2009, Series on Integrated Circuits and Systems.

[15]  Frans P. M. Beenker,et al.  A realistic fault model and test algorithms for static random access memories , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Qiuting Huang,et al.  Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE , 2011, IEEE Journal of Solid-State Circuits.