NoC prototyping on FPGAs: A case study using an image processing benchmark

Network-on-Chip (NoC) approach is emerging as an effective paradigm which addresses the shortcomings of traditional bus-based systems relating to scalability and efficiency for large System-on-Chip (SoC) designs. A significant amount of theoretical work has been done exploring various NoC architectures. But only a handful of studies have demonstrated actual implementation of NoC-based systems for real world applications. These studies provide greater practical insight compared to theoretical studies that rely solely on simulations from traffic generators. Prototyping NoC-based systems for real world applications enables more detailed performance evaluation based on metrics such as area and speed. In this paper, we present a NoC-based Field-Programmable System-on-chip (FPSoC) that is used to implement an image processing benchmark as a real world application. We discuss the challenges of developing an NoC-based system for FPGA implementation and assess the NoC's potential for future development.

[1]  Jih-Sheng Shen,et al.  A low-power crossroad switch architecture and its core placement for network-on-chip , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[2]  Ranga Vemuri,et al.  LiPaR: A light-weight parallel router for FPGA-based networks-on-chip , 2005, ACM Great Lakes Symposium on VLSI.

[3]  Gerard J. M. Smit,et al.  An energy-efficient reconfigurable circuit-switched network-on-chip , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[4]  David A. Sigüenza-Tortosa.  Proteo: The Development of a Practical Network-on-Chip , 2005 .

[5]  Dake Liu,et al.  Design of a system-on-chip switched network and its design support , 2002, IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions.

[6]  Luca Benini,et al.  Networks on chips - technology and tools , 2006, The Morgan Kaufmann series in systems on silicon.

[7]  Dake Liu,et al.  SoCBUS: switched network on chip for hard real time embedded systems , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[8]  Jürgen Teich,et al.  A Dynamic NoC Approach for Communication in Reconfigurable Devices , 2004, FPL.

[9]  M. Horowitz,et al.  Managing wire scaling: a circuit perspective , 2003, Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695).

[10]  Sudhakar Yalamanchili,et al.  Interconnection Networks: An Engineering Approach , 2002 .

[11]  Jürgen Teich,et al.  DyNoC: A dynamic infrastructure for communication in dynamically reconfugurable devices , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[12]  Frank Vahid,et al.  Embedded system design - a unified hardware / software introduction , 2001 .

[13]  Rudy Lauwereins,et al.  Highly scalable network on chip for reconfigurable systems , 2003, Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748).

[14]  Tobias Bjerregaard,et al.  A survey of research and practices of Network-on-chip , 2006, CSUR.

[15]  Barry J. Shepherd,et al.  Graphics file formats - reference and guide , 1994 .

[16]  Brent Nelson,et al.  PNoC: a flexible circuit-switched NoC for FPGA-based systems , 2006 .

[17]  Radu Marculescu,et al.  Challenges and Promising Results in NoC Prototyping Using FPGAs , 2007, IEEE Micro.

[18]  Radu Marculescu,et al.  Key research problems in NoC design: a holistic perspective , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[19]  Luca Benini,et al.  Network-on-chip architectures and design methods , 2005 .

[20]  Rudy Lauwereins,et al.  Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs , 2002, FPL.

[21]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.