Two-dimensional modeling of an ultra-thin body single-gate Si Tunnel-FET
暂无分享,去创建一个
[1] G. Ghibaudo,et al. Modeling of the impact of source/drain regions on short channel effects in MOSFETs , 2013, 2013 14th International Conference on Ultimate Integration on Silicon (ULIS).
[2] Gate-all-around Si nanowire array tunnelling FETs with high on-current of 75 µA/µm @ VDD=1.1V , 2013, 2013 14th International Conference on Ultimate Integration on Silicon (ULIS).
[3] Antonio Gnudi,et al. Drain-conductance optimization in nanowire TFETs , 2012, 2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC).
[4] Byung-Gook Park,et al. Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec , 2007, IEEE Electron Device Letters.
[5] Alexander Kloes,et al. Analytical compact modeling framework for the 2D electrostatics in lightly doped double-gate MOSFETs , 2012 .
[6] S. Horiguchi,et al. Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFETs , 1993, IEEE Electron Device Letters.
[7] K. Nayak,et al. DC Compact Model for SOI Tunnel Field-Effect Transistors , 2012, IEEE Transactions on Electron Devices.
[8] Qin Zhang,et al. Low-Voltage Tunnel Transistors for Beyond CMOS Logic , 2010, Proceedings of the IEEE.
[9] Michael Graef,et al. Two-dimensional physics-based modeling of electrostatics and band-to-band tunneling in tunnel-FETs , 2013, Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013.