An External Capacitor-Less Low-Dropout Voltage Regulator Using a Transconductance Amplifier

This brief presents an external capacitor-less nMOS low-dropout (LDO) voltage regulator integrated with a standard CSMC 0.6-<inline-formula> <tex-math notation="LaTeX">${\mu }\text{m}$ </tex-math></inline-formula> BiCMOS technology. Over a −55 °C to +125 °C temperature range, the fabricated LDO provides a stable and considerable amount of 3 A output current over wide ranges of output capacitance <inline-formula> <tex-math notation="LaTeX">$C_{\mathrm {OUT}}$ </tex-math></inline-formula> (from zero to hundreds of <inline-formula> <tex-math notation="LaTeX">${\mu }\text{F}$ </tex-math></inline-formula>) and effective-series-resistance (ESR) (from tens of milliohms to several ohms). A LDO voltage of 200 mV has been realized by accurate modeling. Operating with an input voltage ranging from 2.2 to 5.5 V provides a scalable output voltage from 0.8 to 3.6 V. When the load current jumps from 100 mA to 3 A within 3 <inline-formula> <tex-math notation="LaTeX">${\mu }\text{s}$ </tex-math></inline-formula>, the output voltage overshoot remains as low as 50 mV without output capacitance, <inline-formula> <tex-math notation="LaTeX">$C_{\mathrm {OUT}}$ </tex-math></inline-formula>. The system bandwidth is about 2 MHz, and hardly changes with load altering to ensure system stability. To improve the load transient response and driving capacity of the nMOS power transistor, a buffer with high input impedance and low output impedance is applied between the transconductance amplifier and the nMOS power transistor. The total area of fabricated LDO voltage regulator chip including pads is 2.1 mm <inline-formula> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 2.2 mm.